From patchwork Wed Aug 17 21:11:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 110362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2C04EB6FA5 for ; Thu, 18 Aug 2011 07:12:22 +1000 (EST) Received: from localhost ([::1]:60035 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QtnPM-0006d0-34 for incoming@patchwork.ozlabs.org; Wed, 17 Aug 2011 17:12:16 -0400 Received: from eggs.gnu.org ([140.186.70.92]:34104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QtnP4-0006Ti-R8 for qemu-devel@nongnu.org; Wed, 17 Aug 2011 17:12:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QtnP2-0003be-Rg for qemu-devel@nongnu.org; Wed, 17 Aug 2011 17:11:58 -0400 Received: from mail-pz0-f42.google.com ([209.85.210.42]:61510) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QtnP2-0003aw-IS for qemu-devel@nongnu.org; Wed, 17 Aug 2011 17:11:56 -0400 Received: by pzk37 with SMTP id 37so2031382pzk.29 for ; Wed, 17 Aug 2011 14:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=CgXhh9vGRXMbIByu0adrVyKSkqpAOwJl0r8fn3I/Iak=; b=PnXTBgqxLTA2cgt/n2fKXLKwbabw2PkzVWQVOG0f5iIGYI72qR4NyRIsQa4S0lhtE9 vi8/JGelUuIlrPhsSWSfpmm2+6SEmUGMzbStMtFGFe8p59G3IZSmgx9ITMdmBjTWbofy 9+YOvs36Bb9EbMQ+1JnicNskNCAnCp0zDMIyQ= Received: by 10.142.139.15 with SMTP id m15mr738607wfd.333.1313615515920; Wed, 17 Aug 2011 14:11:55 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id g4sm901648pbj.9.2011.08.17.14.11.55 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 17 Aug 2011 14:11:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 17 Aug 2011 14:11:45 -0700 Message-Id: <1313615510-10615-2-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1313615510-10615-1-git-send-email-rth@twiddle.net> References: <1313615510-10615-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.42 Subject: [Qemu-devel] [PATCH 1/6] tcg: Add and use TCG_OPF_64BIT. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This allows the simplification of the op_bits function from tcg/optimize.c. Signed-off-by: Richard Henderson --- tcg/optimize.c | 77 ++------------------------------------------ tcg/tcg-opc.h | 98 ++++++++++++++++++++++++++++---------------------------- tcg/tcg.c | 2 +- tcg/tcg.h | 21 ++++++++---- 4 files changed, 67 insertions(+), 131 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 7eb5eb1..98c7e3f 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -92,81 +92,10 @@ static void reset_temp(TCGArg temp, int nb_temps, int nb_globals) } } -static int op_bits(int op) +static int op_bits(enum TCGOpcode op) { - switch (op) { - case INDEX_op_mov_i32: - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: -#ifdef TCG_TARGET_HAS_rot_i32 - case INDEX_op_rotl_i32: - case INDEX_op_rotr_i32: -#endif -#ifdef TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: -#endif -#ifdef TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: -#endif -#ifdef TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: -#endif -#ifdef TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: -#endif -#ifdef TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: -#endif - return 32; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_mov_i64: - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_or_i64: - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: -#ifdef TCG_TARGET_HAS_rot_i64 - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i64: -#endif -#ifdef TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: -#endif -#ifdef TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: -#endif -#ifdef TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: -#endif -#ifdef TCG_TARGET_HAS_ext32s_i64 - case INDEX_op_ext32s_i64: -#endif -#ifdef TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: -#endif -#ifdef TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: -#endif -#ifdef TCG_TARGET_HAS_ext32u_i64 - case INDEX_op_ext32u_i64: -#endif - return 64; -#endif - default: - fprintf(stderr, "Unrecognized operation %d in op_bits.\n", op); - tcg_abort(); - } + const TCGOpDef *def = &tcg_op_defs[op]; + return def->flags & TCG_OPF_64BIT ? 64 : 32; } static int op_to_movi(int op) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 2c7ca1a..b48669b 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -131,98 +131,98 @@ DEF(nor_i32, 1, 2, 0, 0) #endif #if TCG_TARGET_REG_BITS == 64 -DEF(mov_i64, 1, 1, 0, 0) -DEF(movi_i64, 1, 0, 1, 0) -DEF(setcond_i64, 1, 2, 1, 0) +DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT) +DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT) +DEF(setcond_i64, 1, 2, 1, TCG_OPF_64BIT) /* load/store */ -DEF(ld8u_i64, 1, 1, 1, 0) -DEF(ld8s_i64, 1, 1, 1, 0) -DEF(ld16u_i64, 1, 1, 1, 0) -DEF(ld16s_i64, 1, 1, 1, 0) -DEF(ld32u_i64, 1, 1, 1, 0) -DEF(ld32s_i64, 1, 1, 1, 0) -DEF(ld_i64, 1, 1, 1, 0) -DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) -DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) -DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) -DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) +DEF(ld8u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld8s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld16u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld16s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld32u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld32s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) /* arith */ -DEF(add_i64, 1, 2, 0, 0) -DEF(sub_i64, 1, 2, 0, 0) -DEF(mul_i64, 1, 2, 0, 0) +DEF(add_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(sub_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(mul_i64, 1, 2, 0, TCG_OPF_64BIT) #ifdef TCG_TARGET_HAS_div_i64 -DEF(div_i64, 1, 2, 0, 0) -DEF(divu_i64, 1, 2, 0, 0) -DEF(rem_i64, 1, 2, 0, 0) -DEF(remu_i64, 1, 2, 0, 0) +DEF(div_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(divu_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rem_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(remu_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_div2_i64 -DEF(div2_i64, 2, 3, 0, 0) -DEF(divu2_i64, 2, 3, 0, 0) +DEF(div2_i64, 2, 3, 0, TCG_OPF_64BIT) +DEF(divu2_i64, 2, 3, 0, TCG_OPF_64BIT) #endif -DEF(and_i64, 1, 2, 0, 0) -DEF(or_i64, 1, 2, 0, 0) -DEF(xor_i64, 1, 2, 0, 0) +DEF(and_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(or_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(xor_i64, 1, 2, 0, TCG_OPF_64BIT) /* shifts/rotates */ -DEF(shl_i64, 1, 2, 0, 0) -DEF(shr_i64, 1, 2, 0, 0) -DEF(sar_i64, 1, 2, 0, 0) +DEF(shl_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(shr_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(sar_i64, 1, 2, 0, TCG_OPF_64BIT) #ifdef TCG_TARGET_HAS_rot_i64 -DEF(rotl_i64, 1, 2, 0, 0) -DEF(rotr_i64, 1, 2, 0, 0) +DEF(rotl_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rotr_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_deposit_i64 -DEF(deposit_i64, 1, 2, 2, 0) +DEF(deposit_i64, 1, 2, 2, TCG_OPF_64BIT) #endif -DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) +DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) #ifdef TCG_TARGET_HAS_ext8s_i64 -DEF(ext8s_i64, 1, 1, 0, 0) +DEF(ext8s_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext16s_i64 -DEF(ext16s_i64, 1, 1, 0, 0) +DEF(ext16s_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext32s_i64 -DEF(ext32s_i64, 1, 1, 0, 0) +DEF(ext32s_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext8u_i64 -DEF(ext8u_i64, 1, 1, 0, 0) +DEF(ext8u_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext16u_i64 -DEF(ext16u_i64, 1, 1, 0, 0) +DEF(ext16u_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext32u_i64 -DEF(ext32u_i64, 1, 1, 0, 0) +DEF(ext32u_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_bswap16_i64 -DEF(bswap16_i64, 1, 1, 0, 0) +DEF(bswap16_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_bswap32_i64 -DEF(bswap32_i64, 1, 1, 0, 0) +DEF(bswap32_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_bswap64_i64 -DEF(bswap64_i64, 1, 1, 0, 0) +DEF(bswap64_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_not_i64 -DEF(not_i64, 1, 1, 0, 0) +DEF(not_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_neg_i64 -DEF(neg_i64, 1, 1, 0, 0) +DEF(neg_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_andc_i64 -DEF(andc_i64, 1, 2, 0, 0) +DEF(andc_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_orc_i64 -DEF(orc_i64, 1, 2, 0, 0) +DEF(orc_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_eqv_i64 -DEF(eqv_i64, 1, 2, 0, 0) +DEF(eqv_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_nand_i64 -DEF(nand_i64, 1, 2, 0, 0) +DEF(nand_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_nor_i64 -DEF(nor_i64, 1, 2, 0, 0) +DEF(nor_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 92f1989..7179bd4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -68,7 +68,7 @@ static void tcg_target_qemu_prologue(TCGContext *s); static void patch_reloc(uint8_t *code_ptr, int type, tcg_target_long value, tcg_target_long addend); -static TCGOpDef tcg_op_defs[] = { +TCGOpDef tcg_op_defs[] = { #define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags }, #include "tcg-opc.h" #undef DEF diff --git a/tcg/tcg.h b/tcg/tcg.h index e2a7095..6a4f6e4 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -445,13 +445,18 @@ typedef struct TCGArgConstraint { #define TCG_MAX_OP_ARGS 16 -#define TCG_OPF_BB_END 0x01 /* instruction defines the end of a basic - block */ -#define TCG_OPF_CALL_CLOBBER 0x02 /* instruction clobbers call registers - and potentially update globals. */ -#define TCG_OPF_SIDE_EFFECTS 0x04 /* instruction has side effects : it - cannot be removed if its output - are not used */ +/* Bits for TCGOpDef->flags, 8 bits available. */ +enum { + /* Instruction defines the end of a basic block. */ + TCG_OPF_BB_END = 0x01, + /* Instruction clobbers call registers and potentially update globals. */ + TCG_OPF_CALL_CLOBBER = 0x02, + /* Instruction has side effects: it cannot be removed + if its outputs are not used. */ + TCG_OPF_SIDE_EFFECTS = 0x04, + /* Instruction operands are 64-bits (otherwise 32-bits). */ + TCG_OPF_64BIT = 0x08, +}; typedef struct TCGOpDef { const char *name; @@ -463,6 +468,8 @@ typedef struct TCGOpDef { int used; #endif } TCGOpDef; + +extern TCGOpDef tcg_op_defs[]; typedef struct TCGTargetOpDef { TCGOpcode op;