From patchwork Wed Aug 10 22:28:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 109476 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0B659B6F82 for ; Thu, 11 Aug 2011 09:33:18 +1000 (EST) Received: from localhost ([::1]:51942 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QrHHy-0006MR-7L for incoming@patchwork.ozlabs.org; Wed, 10 Aug 2011 18:30:14 -0400 Received: from eggs.gnu.org ([140.186.70.92]:49777) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QrHHI-0004Me-Lb for qemu-devel@nongnu.org; Wed, 10 Aug 2011 18:29:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QrHHH-0006Oq-In for qemu-devel@nongnu.org; Wed, 10 Aug 2011 18:29:32 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:54887) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QrHHH-0006La-CP for qemu-devel@nongnu.org; Wed, 10 Aug 2011 18:29:31 -0400 Received: by mail-ww0-f53.google.com with SMTP id 25so1339901wwf.10 for ; Wed, 10 Aug 2011 15:29:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=ZJ/cjwoo/njSjyoyy4Ebtk19uSGLpo95mol5s7lvaU8=; b=wHIosEchuwyc2BUelPJiujLbI3DW5OYFqRbHu1rpwPLPC8pysv2HqLoZwWscxzR+NU jrySk0G8gpGqSZ3MF24BLw8chVu5wIFnk4bcMVLOWive+LZOjDUrALiEqfVXtGl/N6qp SBX65A/uRWfz1HuFoB83bE8Cq1tf86v7y8vUQ= Received: by 10.216.78.198 with SMTP id g48mr7704757wee.45.1313015370917; Wed, 10 Aug 2011 15:29:30 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id m38sm880619weq.21.2011.08.10.15.29.29 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 10 Aug 2011 15:29:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 10 Aug 2011 15:28:16 -0700 Message-Id: <1313015300-23920-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313015300-23920-1-git-send-email-rth@twiddle.net> References: <1313015300-23920-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.53 Cc: avi@redhat.com Subject: [Qemu-devel] [PATCH 07/11] i8259: Convert to MemoryRegion. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The only non-obvious part is pic_poll_read which used "addr1 >> 7" to detect whether one referred to either the master or slave PIC. Instead, test this directly. Signed-off-by: Richard Henderson --- hw/i8259.c | 65 ++++++++++++++++++++++++++++++++++++++++++----------------- 1 files changed, 46 insertions(+), 19 deletions(-) diff --git a/hw/i8259.c b/hw/i8259.c index 84d330d..8c4feae 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -59,6 +59,8 @@ typedef struct PicState { uint8_t elcr; /* PIIX edge/trigger selection*/ uint8_t elcr_mask; PicState2 *pics_state; + MemoryRegion base_io; + MemoryRegion elcr_io; } PicState; struct PicState2 { @@ -284,13 +286,15 @@ static void pic_reset(void *opaque) /* Note: ELCR is not reset */ } -static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) +static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, + uint64_t val64, unsigned size) { PicState *s = opaque; + uint32_t addr = addr64; + uint32_t val = val64; int priority, cmd, irq; DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val); - addr &= 1; if (addr == 0) { if (val & 0x10) { /* init */ @@ -374,19 +378,21 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) } } -static uint32_t pic_poll_read (PicState *s, uint32_t addr1) +static uint32_t pic_poll_read(PicState *s) { int ret; ret = pic_get_irq(s); if (ret >= 0) { - if (addr1 >> 7) { + bool slave = (s == &isa_pic->pics[1]); + + if (slave) { s->pics_state->pics[0].isr &= ~(1 << 2); s->pics_state->pics[0].irr &= ~(1 << 2); } s->irr &= ~(1 << ret); s->isr &= ~(1 << ret); - if (addr1 >> 7 || ret != 2) + if (slave || ret != 2) pic_update_irq(s->pics_state); } else { ret = 0x07; @@ -396,16 +402,15 @@ static uint32_t pic_poll_read (PicState *s, uint32_t addr1) return ret; } -static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) +static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1, + unsigned size) { PicState *s = opaque; - unsigned int addr; + unsigned int addr = addr1; int ret; - addr = addr1; - addr &= 1; if (s->poll) { - ret = pic_poll_read(s, addr1); + ret = pic_poll_read(s); s->poll = 0; } else { if (addr == 0) { @@ -417,7 +422,7 @@ static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) ret = s->imr; } } - DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret); + DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret); return ret; } @@ -427,22 +432,24 @@ uint32_t pic_intack_read(PicState2 *s) { int ret; - ret = pic_poll_read(&s->pics[0], 0x00); + ret = pic_poll_read(&s->pics[0]); if (ret == 2) - ret = pic_poll_read(&s->pics[1], 0x80) + 8; + ret = pic_poll_read(&s->pics[1]) + 8; /* Prepare for ISR read */ s->pics[0].read_reg_select = 1; return ret; } -static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) +static void elcr_ioport_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { PicState *s = opaque; s->elcr = val & s->elcr_mask; } -static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) +static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PicState *s = opaque; return s->elcr; @@ -474,15 +481,35 @@ static const VMStateDescription vmstate_pic = { } }; +static const MemoryRegionOps pic_base_ioport_ops = { + .read = pic_ioport_read, + .write = pic_ioport_write, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static const MemoryRegionOps pic_elcr_ioport_ops = { + .read = elcr_ioport_read, + .write = elcr_ioport_write, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + /* XXX: add generic master/slave system */ static void pic_init1(int io_addr, int elcr_addr, PicState *s) { - register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); - register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); + memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2); + memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1); + + isa_register_ioport(NULL, &s->base_io, io_addr); if (elcr_addr >= 0) { - register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); - register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); + isa_register_ioport(NULL, &s->elcr_io, elcr_addr); } + vmstate_register(NULL, io_addr, &vmstate_pic, s); qemu_register_reset(pic_reset, s); }