From patchwork Fri Jun 24 19:23:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 101896 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D2793B6F8E for ; Sat, 25 Jun 2011 06:54:26 +1000 (EST) Received: from localhost ([::1]:54535 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QaDOR-0005pE-PS for incoming@patchwork.ozlabs.org; Fri, 24 Jun 2011 16:54:24 -0400 Received: from eggs.gnu.org ([140.186.70.92]:52472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QaBzQ-0007sf-3y for qemu-devel@nongnu.org; Fri, 24 Jun 2011 15:24:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QaBzN-0000rq-00 for qemu-devel@nongnu.org; Fri, 24 Jun 2011 15:24:27 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:61113) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QaBzM-0000pt-Ak for qemu-devel@nongnu.org; Fri, 24 Jun 2011 15:24:24 -0400 Received: by mail-wy0-f173.google.com with SMTP id 28so2380750wyf.4 for ; Fri, 24 Jun 2011 12:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=3yOZJ9XlJgyVxKYimBg3H9pfLa3BruDy+j+M+4vX7S4=; b=V1zyTsQEHN2O0bzWypDh0ecotIxPr9e0wlmr4nqKtn183Uai87J3s7JN/wBtfn4OM3 nC38EeKcMxFXfs950b9ACHPU9+cbtwT7fY3TC8Cpcf99brDLnf4ZlfPPOCRaswYUfE7M VrZH8ze5ewwIrDQK6+m2bQhbM0mDXcBey0rPQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=I5AQPbIFjzWTTo+8UBXJV+hFlLQfgHMHO1bky8SR96SAOjFw+XFBnbg60yAur+5RKF U8Kj7d8aOE+Z1YMhViphyXbJEOraLES8tuXGXWR7RD6TePF8DiM6QQB59432F1RLDsrA ShJ4n1c5cvheDfJG1qo3dgV2w+CO0PR4SALfo= Received: by 10.227.198.10 with SMTP id em10mr3357924wbb.108.1308943463941; Fri, 24 Jun 2011 12:24:23 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id ex2sm2224860wbb.14.2011.06.24.12.24.21 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Jun 2011 12:24:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 24 Jun 2011 12:23:54 -0700 Message-Id: <1308943435-24993-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1308943435-24993-1-git-send-email-rth@twiddle.net> References: <1308943435-24993-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.173 Subject: [Qemu-devel] [PATCH 7/8] target-alpha: Add high-resolution access to wall clock and an alarm. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The alarm is a fully general one-shot time comparator, which will be usable under Linux as a hrtimer source. It's much more flexible than the RTC source available on real hardware. The wall clock allows the guest access to the host timekeeping. Much like the KVM wall clock source for other guests. Both are accessed via the PALcode Cserve entry point. Signed-off-by: Richard Henderson --- hw/alpha_typhoon.c | 22 ++++++++++++++++++++-- target-alpha/cpu.h | 4 ++++ target-alpha/helper.h | 4 ++++ target-alpha/op_helper.c | 15 +++++++++++++++ target-alpha/translate.c | 14 ++++++++++++++ 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index 7cdf7d3..731b6ea 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -681,6 +681,16 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) } } +static void typhoon_alarm_timer(void *opaque) +{ + TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3); + int cpu = (uintptr_t)opaque & 3; + + /* Set the ITI bit for this cpu. */ + s->cchip.misc |= 1 << (cpu + 4); + cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER); +} + PCIBus *typhoon_init(qemu_irq *p_isa_irq, qemu_irq *p_rtc_irq, CPUState *cpus[3], pci_map_irq_fn sys_map_irq) { @@ -689,14 +699,22 @@ PCIBus *typhoon_init(qemu_irq *p_isa_irq, qemu_irq *p_rtc_irq, PCIHostState *p; TyphoonState *s; PCIBus *b; - int region; + int i, region; dev = qdev_create(NULL, "typhoon-pcihost"); p = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); s = container_of(p, TyphoonState, host); /* Remember the CPUs so that we can deliver interrupts to them. */ - memcpy(s->cchip.cpu, cpus, 4 * sizeof(CPUState *)); + for (i = 0; i < 4; i++) { + CPUState *env = cpus[i]; + s->cchip.cpu[i] = env; + if (env) { + env->alarm_timer = qemu_new_timer_ns(rtc_clock, + typhoon_alarm_timer, + (void *)((uintptr_t)s + i)); + } + } *p_isa_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1); *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1); diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index e98b325..2a8b99a 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -267,6 +267,10 @@ struct CPUAlphaState { uint64_t scratch[24]; #endif + /* This alarm doesn't exist in real hardware; we wish it did. */ + struct QEMUTimer *alarm_timer; + uint64_t alarm_expire; + #if TARGET_LONG_BITS > HOST_LONG_BITS /* temporary fixed-point registers * used to emulate 64 bits target on 32 bits hosts diff --git a/target-alpha/helper.h b/target-alpha/helper.h index c352c24..b693cee 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -113,7 +113,11 @@ DEF_HELPER_2(stq_c_phys, i64, i64, i64) DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) + DEF_HELPER_1(halt, void, i64); + +DEF_HELPER_FLAGS_0(get_time, TCG_CALL_CONST, i64) +DEF_HELPER_FLAGS_1(set_alarm, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 80656f5..c37fb5f 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1225,6 +1225,21 @@ void helper_halt(uint64_t restart) qemu_system_shutdown_request(); } } + +uint64_t helper_get_time(void) +{ + return qemu_get_clock_ns(rtc_clock); +} + +void helper_set_alarm(uint64_t expire) +{ + if (expire) { + env->alarm_expire = expire; + qemu_mod_timer(env->alarm_timer, expire); + } else { + qemu_del_timer(env->alarm_timer); + } +} #endif /*****************************************************************************/ diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 1a66322..1b2a56e 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1591,6 +1591,9 @@ static int cpu_pr_data(int pr) return offsetof(CPUAlphaState, shadow[pr - 32]); case 40 ... 63: return offsetof(CPUAlphaState, scratch[pr - 40]); + + case 251: + return offsetof(CPUAlphaState, alarm_expire); } return 0; } @@ -1605,6 +1608,12 @@ static void gen_mfpr(int ra, int regno) return; } + if (regno == 250) { + /* WALL_TIME */ + gen_helper_get_time(cpu_ir[ra]); + return; + } + /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ if (data == 0) { @@ -1651,6 +1660,11 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) gen_helper_halt(tmp); return EXIT_PC_STALE; + case 251: + /* ALARM */ + gen_helper_set_alarm(tmp); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */