From patchwork Fri Jun 24 19:23:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 101882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BCFE9B6F83 for ; Sat, 25 Jun 2011 05:48:59 +1000 (EST) Received: from localhost ([::1]:51678 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QaCN5-0004vI-1N for incoming@patchwork.ozlabs.org; Fri, 24 Jun 2011 15:48:55 -0400 Received: from eggs.gnu.org ([140.186.70.92]:52426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QaBzL-0007rR-1g for qemu-devel@nongnu.org; Fri, 24 Jun 2011 15:24:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QaBzI-0000r0-AX for qemu-devel@nongnu.org; Fri, 24 Jun 2011 15:24:23 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:61113) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QaBzH-0000pt-Va for qemu-devel@nongnu.org; Fri, 24 Jun 2011 15:24:20 -0400 Received: by mail-wy0-f173.google.com with SMTP id 28so2380750wyf.4 for ; Fri, 24 Jun 2011 12:24:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=DbkFQzU5H8IY0Ka99Fv3ZS74jziTJGUQmKsbRj9n+mU=; b=jvcCBcLIG6yq+uBmCr5XEfMCS1D70dtmjyRLBqoOIM7hVz2BPvHXE6bRFmT+fGFsXe ORIxuMw8TkNpv5eC1tiUYTdCiD7Cdz8jOEgL4qAw+plykkl8iLlODQ2tq4+ekIABhASq uQB0Upin0QPdzx47So6lOMmMMrqkheZxjZzoA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=rEkIfOvQjBBNYawpYEJSMUVxRZBwJQXxlXLl5hEjLrcoxP6Xpn0joa+x5YEMTtecKq uKgNV1e5Rb6bkpEFry8U26XX0T2d4jsg1qOm2nRS1cvYbmT0S1yj/57tkM1vhEzKp0am d/d4J4mWn+EpvxVh/kCjLngJy5SGLTE9zLsnU= Received: by 10.227.54.6 with SMTP id o6mr3364553wbg.61.1308943459617; Fri, 24 Jun 2011 12:24:19 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id ex2sm2224860wbb.14.2011.06.24.12.24.17 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Jun 2011 12:24:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 24 Jun 2011 12:23:52 -0700 Message-Id: <1308943435-24993-6-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1308943435-24993-1-git-send-email-rth@twiddle.net> References: <1308943435-24993-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.173 Subject: [Qemu-devel] [PATCH 5/8] target-alpha: Implement WAIT IPR. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org --- target-alpha/translate.c | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 936760c..e13ac30 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1618,9 +1618,10 @@ static void gen_mfpr(int ra, int regno) } } -static void gen_mtpr(int rb, int regno) +static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) { TCGv tmp; + int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1628,19 +1629,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* These two register numbers perform a TLB cache flush. Thankfully we - can only do this inside PALmode, which means that the current basic - block cannot be affected by the change in mappings. */ - if (regno == 255) { + switch (regno) { + case 255: /* TBIA */ gen_helper_tbia(); - } else if (regno == 254) { + break; + + case 254: /* TBIS */ gen_helper_tbis(tmp); - } else { + break; + + case 253: + /* WAIT */ + tmp = tcg_const_i64(1); + tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted)); + return gen_excp(ctx, EXCP_HLT, 0); + + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ - int data = cpu_pr_data(regno); + data = cpu_pr_data(regno); if (data != 0) { if (data & PR_BYTE) { tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); @@ -1650,11 +1659,14 @@ static void gen_mtpr(int rb, int regno) tcg_gen_st_i64(tmp, cpu_env, data); } } + break; } if (rb == 31) { tcg_temp_free(tmp); } + + return NO_EXIT; } #endif /* !USER_ONLY*/ @@ -3054,8 +3066,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) /* HW_MTPR (PALcode) */ #ifndef CONFIG_USER_ONLY if (ctx->tb->flags & TB_FLAGS_PAL_MODE) { - gen_mtpr(rb, insn & 0xffff); - break; + return gen_mtpr(ctx, rb, insn & 0xffff); } #endif goto invalid_opc;