From patchwork Mon May 23 20:28:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 97035 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DE6A2B6FBA for ; Tue, 24 May 2011 06:29:22 +1000 (EST) Received: from localhost ([::1]:49490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObke-0004ae-5K for incoming@patchwork.ozlabs.org; Mon, 23 May 2011 16:29:20 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkJ-0004Uu-4a for qemu-devel@nongnu.org; Mon, 23 May 2011 16:28:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QObkI-0008HV-72 for qemu-devel@nongnu.org; Mon, 23 May 2011 16:28:59 -0400 Received: from mail-gy0-f173.google.com ([209.85.160.173]:59083) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkI-0008HM-3P for qemu-devel@nongnu.org; Mon, 23 May 2011 16:28:58 -0400 Received: by gyg4 with SMTP id 4so2710878gyg.4 for ; Mon, 23 May 2011 13:28:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=OO61Vltf75QAMzHI9ncsWUkY/a65rMHtO4sd+YSOWy0=; b=bLle4wPFoNnFebnrSaQKCMrstKkH1dOQKinkz6CJaGW4mnMmkK6+1UANAvUDe3Ay+L a4KYuuJ4LEpUWUzn3N9t2cmKwC7nr+PqwdWKrGiN2TSpsmGOpKBRKcDypHD7iEEowF1Z /4Sm/qnyEXxmPnq1P9OBKXcPM0L242Pn/87ZY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=imM+ezl1IqnDiL5mOWHrExRQEjUG5LBNyR/oKgao8+9SogQpkCVR/rm3I9+p7k8KMC 7Ed8QwNadKoOH+WLPCf92XaCtzSKGHQt1ANvoBqCBvvDY6Yd/B9sW+gaLz5U1bW5VGJk TeRNCuvQ/O14dFj4RqIEdJh2aGQ+w8mha3jdk= Received: by 10.101.10.17 with SMTP id n17mr4584329ani.34.1306182537438; Mon, 23 May 2011 13:28:57 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id e9sm5033668ann.24.2011.05.23.13.28.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 23 May 2011 13:28:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 23 May 2011 13:28:22 -0700 Message-Id: <1306182526-12081-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1306182526-12081-1-git-send-email-rth@twiddle.net> References: <1306182526-12081-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.160.173 Subject: [Qemu-devel] [PATCH 02/26] target-alpha: Disassemble EV6 PALcode instructions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The QEMU emulation PALcode will use EV6 PALcode insns regardless of the "real" cpu instruction set being emulated. Signed-off-by: Richard Henderson --- alpha-dis.c | 4 ---- dis-asm.h | 3 +++ disas.c | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/alpha-dis.c b/alpha-dis.c index 8a2411e..ae331b3 100644 --- a/alpha-dis.c +++ b/alpha-dis.c @@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands; #define AXP_REG_SP 30 #define AXP_REG_ZERO 31 -#define bfd_mach_alpha_ev4 0x10 -#define bfd_mach_alpha_ev5 0x20 -#define bfd_mach_alpha_ev6 0x30 - enum bfd_reloc_code_real { BFD_RELOC_23_PCREL_S2, BFD_RELOC_ALPHA_HINT diff --git a/dis-asm.h b/dis-asm.h index 296537a..5b07d7f 100644 --- a/dis-asm.h +++ b/dis-asm.h @@ -184,6 +184,9 @@ enum bfd_architecture #define bfd_mach_sh5 0x50 bfd_arch_alpha, /* Dec Alpha */ #define bfd_mach_alpha 1 +#define bfd_mach_alpha_ev4 0x10 +#define bfd_mach_alpha_ev5 0x20 +#define bfd_mach_alpha_ev6 0x30 bfd_arch_arm, /* Advanced Risc Machines ARM */ #define bfd_mach_arm_unknown 0 #define bfd_mach_arm_2 1 diff --git a/disas.c b/disas.c index 223606c..d208c52 100644 --- a/disas.c +++ b/disas.c @@ -205,7 +205,7 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) disasm_info.mach = bfd_mach_sh4; print_insn = print_insn_sh; #elif defined(TARGET_ALPHA) - disasm_info.mach = bfd_mach_alpha; + disasm_info.mach = bfd_mach_alpha_ev6; print_insn = print_insn_alpha; #elif defined(TARGET_CRIS) if (flags != 32) {