From patchwork Mon May 23 14:40:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 96954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0B13AB6F9A for ; Tue, 24 May 2011 00:43:06 +1000 (EST) Received: from localhost ([::1]:55635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOWLX-0003pG-6H for incoming@patchwork.ozlabs.org; Mon, 23 May 2011 10:43:03 -0400 Received: from eggs.gnu.org ([140.186.70.92]:46114) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOWJq-0001Mn-RB for qemu-devel@nongnu.org; Mon, 23 May 2011 10:41:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QOWJo-0001Mk-En for qemu-devel@nongnu.org; Mon, 23 May 2011 10:41:18 -0400 Received: from smtp.ispras.ru ([83.149.198.202]:37598) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOWJo-0001Lw-2I for qemu-devel@nongnu.org; Mon, 23 May 2011 10:41:16 -0400 Received: from bulbul.intra.ispras.ru (winnie.ispras.ru [83.149.198.236]) by smtp.ispras.ru (Postfix) with ESMTP id 5F3D05D40C6; Mon, 23 May 2011 18:37:20 +0400 (MSD) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Mon, 23 May 2011 18:40:54 +0400 Message-Id: <1306161654-4388-9-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1306161654-4388-1-git-send-email-batuzovk@ispras.ru> References: <1306161654-4388-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 83.149.198.202 Cc: zhur@ispras.ru Subject: [Qemu-devel] [RFC][PATCH v0 8/8] Add spill count profiling. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Gather generated spills statistics. It is useful for debugging and evaluating of new register allocator. Signed-off-by: Kirill Batuzov --- tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg.h | 6 +++++ 2 files changed, 75 insertions(+), 0 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 022eef9..ba2cddc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1530,6 +1530,11 @@ static void temp_allocate_frame(TCGContext *s, int temp) s->current_frame_offset += sizeof(tcg_target_long); } +#ifdef CONFIG_PROFILER +enum { SPILL_REAL, SPILL_BB_END, SPILL_CALL_HWREG, + SPILL_CALL_IARG, SPILL_CALL_CLOBBER } spill_cause; +#endif + /* free register 'reg' by spilling the corresponding temporary if necessary */ static void tcg_reg_free(TCGContext *s, int reg) { @@ -1544,6 +1549,26 @@ static void tcg_reg_free(TCGContext *s, int reg) if (!ts->mem_allocated) temp_allocate_frame(s, temp); tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset); +#ifdef CONFIG_PROFILER + s->spill_count++; + switch (spill_cause) { + case SPILL_REAL: + s->spill_real++; + break; + case SPILL_BB_END: + s->spill_bb_end++; + break; + case SPILL_CALL_HWREG: + s->spill_call_hwreg++; + break; + case SPILL_CALL_IARG: + s->spill_call_iarg++; + break; + case SPILL_CALL_CLOBBER: + s->spill_call_clobber++; + break; + } +#endif } ts->val_type = TEMP_VAL_MEM; s->reg_to_temp[reg] = -1; @@ -1582,6 +1607,9 @@ static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2) } } #else +#ifdef CONFIG_PROFILER + spill_cause = SPILL_REAL; +#endif tcg_reg_free(s, reg); return reg; #endif @@ -1590,6 +1618,9 @@ static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2) #ifdef USE_ADVANCED_REGALLOC if (best_score >= 0 && best_reg >= 0) { +#ifdef CONFIG_PROFILER + spill_cause = SPILL_REAL; +#endif tcg_reg_free(s, best_reg); return best_reg; } @@ -1653,6 +1684,9 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) for(i = s->nb_globals; i < s->nb_temps; i++) { ts = &s->temps[i]; if (ts->temp_local) { +#ifdef CONFIG_PROFILER + spill_cause = SPILL_BB_END; +#endif temp_save(s, i, allocated_regs); } else { if (ts->val_type == TEMP_VAL_REG) { @@ -1662,6 +1696,10 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) } } +#ifdef CONFIG_PROFILER + spill_cause = SPILL_BB_END; +#endif + save_globals(s, allocated_regs); } @@ -1860,12 +1898,18 @@ static void tcg_reg_alloc_op(TCGContext *s, /* XXX: permit generic clobber register list ? */ for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) { if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) { +#ifdef CONFIG_PROFILER + spill_cause = SPILL_CALL_CLOBBER; +#endif tcg_reg_free(s, reg); } } /* XXX: for load/store we could do that only for the slow path (i.e. when a memory callback is called) */ +#ifdef CONFIG_PROFILER + spill_cause = SPILL_CALL_HWREG; +#endif /* store globals and free associated registers (we assume the insn can modify any global. */ save_globals(s, allocated_regs); @@ -2001,6 +2045,9 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def, if (arg != TCG_CALL_DUMMY_ARG) { ts = &s->temps[arg]; reg = tcg_target_call_iarg_regs[i]; +#ifdef CONFIG_PROFILER + spill_cause = SPILL_CALL_IARG; +#endif tcg_reg_free(s, reg); if (ts->val_type == TEMP_VAL_REG) { if (ts->reg != reg) { @@ -2071,6 +2118,9 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def, /* clobber call registers */ for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) { if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) { +#ifdef CONFIG_PROFILER + spill_cause = SPILL_CALL_CLOBBER; +#endif tcg_reg_free(s, reg); } } @@ -2078,6 +2128,9 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def, /* store globals and free associated registers (we assume the call can modify any global. */ if (!(flags & TCG_CALL_CONST)) { +#ifdef CONFIG_PROFILER + spill_cause = SPILL_CALL_HWREG; +#endif save_globals(s, allocated_regs); } @@ -2209,6 +2262,14 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf, if (args[0] < s->nb_globals) { if (tcg_op_defs[gen_opc_buf[param_next_use_ptr[0]]].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_BB_END)) { +#ifdef CONFIG_PROFILER + if (tcg_op_defs[gen_opc_buf[param_next_use_ptr[0]]].flags + & TCG_OPF_CALL_CLOBBER) { + spill_cause = SPILL_CALL_HWREG; + } else { + spill_cause = SPILL_BB_END; + } +#endif tcg_reg_free(s, s->temps[args[0]].reg); } } @@ -2354,6 +2415,14 @@ void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) s->restore_count); cpu_fprintf(f, " avg cycles %0.1f\n", s->restore_count ? (double)s->restore_time / s->restore_count : 0); + cpu_fprintf(f, "spill count %" PRId64 "\n", + s->spill_count); + cpu_fprintf(f, " real spills %" PRId64 "\n", s->spill_real); + cpu_fprintf(f, " spills at bb end %" PRId64 "\n", s->spill_bb_end); + cpu_fprintf(f, " spills at call:\n"); + cpu_fprintf(f, " globals %" PRId64 "\n", s->spill_call_hwreg); + cpu_fprintf(f, " iarg passing %" PRId64 "\n", s->spill_call_iarg); + cpu_fprintf(f, " call cloobers %" PRId64 "\n", s->spill_call_clobber); dump_op_count(); } diff --git a/tcg/tcg.h b/tcg/tcg.h index 9ff519e..722bd72 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -328,6 +328,12 @@ struct TCGContext { int64_t la_time; int64_t restore_count; int64_t restore_time; + int64_t spill_count; + int64_t spill_bb_end; + int64_t spill_call_hwreg; + int64_t spill_call_iarg; + int64_t spill_call_clobber; + int64_t spill_real; #endif #ifdef CONFIG_DEBUG_TCG