From patchwork Mon May 9 21:34:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 94879 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8A367B6F11 for ; Tue, 10 May 2011 07:43:50 +1000 (EST) Received: from localhost ([::1]:42976 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJYF1-0001HH-VR for incoming@patchwork.ozlabs.org; Mon, 09 May 2011 17:43:47 -0400 Received: from eggs.gnu.org ([140.186.70.92]:38609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6r-0003sZ-Ox for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJY6q-0006Nr-Ss for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:21 -0400 Received: from mail-iw0-f173.google.com ([209.85.214.173]:38418) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6q-0006Af-P7 for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:20 -0400 Received: by mail-iw0-f173.google.com with SMTP id 42so5560360iwl.4 for ; Mon, 09 May 2011 14:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=vEDqgIHLLfAZ9M6GmjiC+0i7zpIR5t5rLUhtY9yCwTg=; b=eNa+7+825XCU7pLDx6gnzT4o7rxBPk3tqHyGla/hw8MQQF7hOeLVD+XDi7eJea5PA5 yabAyb2cUBH5DxGNLsveSYpEBRLKu/BZWZwugHzM8hzEhgBQ2oAvbZOPQZLtoLDkvN/B tFLhsBlAF0rIlrOwYt2oUyyws4AnU7SmHjsJk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=fpKbyPafhEsqDfmqK/le47iL75A57B2342N41pWV3dyBiI9DHsQvxYp4aajivpfpDP 53Mgm8Qx5+rXUumLUdPXmxSLFeRwYiYKzBoIFWZT1q8hJT9t8RnW05Yhpn+zhoNV4rCN QO5R5Cu2jb8kO98S1idYmnb1u6slof8QfP7Gc= Received: by 10.42.217.3 with SMTP id hk3mr6786858icb.200.1304976920531; Mon, 09 May 2011 14:35:20 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id ui7sm2549819icb.14.2011.05.09.14.35.19 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 09 May 2011 14:35:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 May 2011 14:34:41 -0700 Message-Id: <1304976889-29675-28-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304976889-29675-1-git-send-email-rth@twiddle.net> References: <1304976889-29675-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.214.173 Subject: [Qemu-devel] [PATCH 27/35] target-alpha: Implement TLB flush primitives. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Expose these via MTPR, more or less like the real HW does. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 3 +++ target-alpha/op_helper.c | 11 ++++++++++- target-alpha/translate.c | 32 +++++++++++++++++++++----------- 3 files changed, 34 insertions(+), 12 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 9ffc372..2dec57e 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -110,6 +110,9 @@ DEF_HELPER_2(stl_phys, void, i64, i64) DEF_HELPER_2(stq_phys, void, i64, i64) DEF_HELPER_2(stl_c_phys, i64, i64, i64) DEF_HELPER_2(stq_c_phys, i64, i64, i64) + +DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) +DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 36b8289..d332719 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1205,6 +1205,16 @@ void helper_hw_ret (uint64_t a) swap_shadow_regs(env); } } + +void helper_tbia(void) +{ + tlb_flush(env, 1); +} + +void helper_tbis(uint64_t p) +{ + tlb_flush_page(env, p); +} #endif /*****************************************************************************/ @@ -1335,5 +1345,4 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) } env = saved_env; } - #endif diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 8b9dded..8107d19 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1624,7 +1624,6 @@ static void gen_mfpr(int ra, int regno) static void gen_mtpr(int rb, int regno) { TCGv tmp; - int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1632,16 +1631,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* The basic registers are data only, and unknown registers - are read-zero, write-ignore. */ - data = cpu_pr_data(regno); - if (data != 0) { - if (data & PR_BYTE) { - tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); - } else if (data & PR_LONG) { - tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); - } else { - tcg_gen_st_i64(tmp, cpu_env, data); + /* These two register numbers perform a TLB cache flush. Thankfully we + can only do this inside PALmode, which means that the current basic + block cannot be affected by the change in mappings. */ + if (regno == 255) { + /* TBIA */ + gen_helper_tbia(); + } else if (regno == 254) { + /* TBIS */ + gen_helper_tbis(tmp); + } else { + /* The basic registers are data only, and unknown registers + are read-zero, write-ignore. */ + int data = cpu_pr_data(regno); + if (data != 0) { + if (data & PR_BYTE) { + tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); + } else if (data & PR_LONG) { + tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); + } else { + tcg_gen_st_i64(tmp, cpu_env, data); + } } }