From patchwork Mon May 9 21:34:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 94882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0E4F7B6F17 for ; Tue, 10 May 2011 07:44:45 +1000 (EST) Received: from localhost ([::1]:46066 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJYFu-0002xb-4g for incoming@patchwork.ozlabs.org; Mon, 09 May 2011 17:44:42 -0400 Received: from eggs.gnu.org ([140.186.70.92]:38539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6n-0003l4-Gi for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJY6m-0006MF-19 for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:17 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:48729) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6l-0006A3-UF for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:15 -0400 Received: by mail-iy0-f173.google.com with SMTP id 10so5564538iym.4 for ; Mon, 09 May 2011 14:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=npW3LfJtrVYrPipMLoP025zmkoKBk+jGgQZVw35BYw0=; b=G0vWavOGhj6lz8ncSG3QwE0uf79lZZbRGov9oJNP544ratKbjrAt5csKu9Ffzlfmu7 9lIsS5PAYb0flxxumlyHlVkQRXFrOzOOu9eCQBOz0dzbl9fN6K6csEpnoRImFq8LmNb0 nYkWFAb+U72qQ997rgYhMM6EgqZQXTjudZZCE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=KJXvSeu368dxGM6tyBhd4CVOIFg2csDD40vq5UOqhuBl7cmfnYO4A53XEz7S+qZTN5 cffm1FlPBoa6chCpWPFodG3ZyP805KPbgtPd5V9tUAsQSH9JI32MJWh5zE3CD/EnXaxJ GUpckthS5Mn+LLbt5a9U0xqzm0XUBFTQv4lfg= Received: by 10.42.162.69 with SMTP id w5mr1377236icx.48.1304976915682; Mon, 09 May 2011 14:35:15 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id ui7sm2549819icb.14.2011.05.09.14.35.14 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 09 May 2011 14:35:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 May 2011 14:34:35 -0700 Message-Id: <1304976889-29675-22-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304976889-29675-1-git-send-email-rth@twiddle.net> References: <1304976889-29675-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.173 Subject: [Qemu-devel] [PATCH 21/35] target-alpha: Implement more CALL_PAL values inline. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In particular, SWPIPL is used quite a lot by the Linux kernel. Doing this inline makes it significantly easier to step through without the debugger getting confused by the mode switch. Signed-off-by: Richard Henderson --- target-alpha/translate.c | 141 ++++++++++++++++++++++++++++++++++++---------- 1 files changed, 110 insertions(+), 31 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 28ccf6b..8b9dded 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -85,8 +85,10 @@ static TCGv cpu_pc; static TCGv cpu_lock_addr; static TCGv cpu_lock_st_addr; static TCGv cpu_lock_value; -#ifdef CONFIG_USER_ONLY -static TCGv cpu_uniq; +static TCGv cpu_unique; +#ifndef CONFIG_USER_ONLY +static TCGv cpu_sysval; +static TCGv cpu_usp; #endif /* register names */ @@ -131,9 +133,13 @@ static void alpha_translate_init(void) offsetof(CPUState, lock_value), "lock_value"); -#ifdef CONFIG_USER_ONLY - cpu_uniq = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, unique), "uniq"); + cpu_unique = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, unique), "unique"); +#ifndef CONFIG_USER_ONLY + cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, sysval), "sysval"); + cpu_usp = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, usp), "usp"); #endif /* register helpers */ @@ -1464,6 +1470,104 @@ static void gen_rx(int ra, int set) tcg_temp_free_i32(tmp); } +static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) +{ + /* We're emulating OSF/1 PALcode. Many of these are trivial access + to internal cpu registers. */ + + /* Unprivileged PAL call */ + if (palcode >= 0x80 && palcode < 0xC0) { + switch (palcode) { + case 0x86: + /* IMB */ + /* No-op inside QEMU. */ + break; + case 0x9E: + /* RDUNIQUE */ + tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_unique); + break; + case 0x9F: + /* WRUNIQUE */ + tcg_gen_mov_i64(cpu_unique, cpu_ir[IR_A0]); + break; + default: + return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xbf); + } + return NO_EXIT; + } + +#ifndef CONFIG_USER_ONLY + /* Privileged PAL code */ + if (palcode < 0x40 && (ctx->tb->flags & TB_FLAGS_USER_MODE) == 0) { + switch (palcode) { + case 0x01: + /* CFLUSH */ + /* No-op inside QEMU. */ + break; + case 0x02: + /* DRAINA */ + /* No-op inside QEMU. */ + break; + case 0x2D: + /* WRVPTPTR */ + tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vptptr)); + break; + case 0x31: + /* WRVAL */ + tcg_gen_mov_i64(cpu_sysval, cpu_ir[IR_A0]); + break; + case 0x32: + /* RDVAL */ + tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_sysval); + break; + + case 0x35: { + /* SWPIPL */ + TCGv tmp; + + /* Note that we already know we're in kernel mode, so we know + that PS only contains the 3 IPL bits. */ + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps)); + + /* But make sure and store only the 3 IPL bits from the user. */ + tmp = tcg_temp_new(); + tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK); + tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps)); + tcg_temp_free(tmp); + break; + } + + case 0x36: + /* RDPS */ + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, + offsetof(CPUAlphaState, ps)); + break; + case 0x38: + /* WRUSP */ + tcg_gen_mov_i64(cpu_usp, cpu_ir[IR_A0]); + break; + case 0x3A: + /* RDUSP */ + tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_usp); + break; + + /* TODO: + 0x3C Whami + These merely need more cooperation in designation of + internal processor registers w/ palcode. These are + currently stored in palcode scratch registers and + should be treated like UNIQUE. */ + + default: + return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3f); + } + return NO_EXIT; + } +#endif + + return gen_invalid(ctx); +} + #ifndef CONFIG_USER_ONLY #define PR_BYTE 0x100000 @@ -1582,32 +1686,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) switch (opc) { case 0x00: /* CALL_PAL */ -#ifdef CONFIG_USER_ONLY - if (palcode == 0x9E) { - /* RDUNIQUE */ - tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_uniq); - break; - } else if (palcode == 0x9F) { - /* WRUNIQUE */ - tcg_gen_mov_i64(cpu_uniq, cpu_ir[IR_A0]); - break; - } -#endif - if (palcode >= 0x80 && palcode < 0xC0) { - /* Unprivileged PAL call */ - ret = gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xBF); - break; - } -#ifndef CONFIG_USER_ONLY - if (palcode < 0x40) { - /* Privileged PAL code */ - if (ctx->mem_idx & 1) - goto invalid_opc; - ret = gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3F); - } -#endif - /* Invalid PAL call */ - goto invalid_opc; + return gen_call_pal(ctx, palcode); case 0x01: /* OPC01 */ goto invalid_opc;