From patchwork Mon May 9 21:34:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 94872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 80381B6F18 for ; Tue, 10 May 2011 07:41:32 +1000 (EST) Received: from localhost ([::1]:35493 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJYCn-0005hq-QA for incoming@patchwork.ozlabs.org; Mon, 09 May 2011 17:41:29 -0400 Received: from eggs.gnu.org ([140.186.70.92]:38523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6m-0003jK-EX for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJY6l-0006M7-Fb for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:16 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:48729) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6l-0006A3-7C for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:15 -0400 Received: by mail-iy0-f173.google.com with SMTP id 10so5564538iym.4 for ; Mon, 09 May 2011 14:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=ulhrV01tM7d70ydagauFoatL2DKchkrhJwbT0UYm4iM=; b=t+92gTxiD8MaIo+jkK7RzpTbSt2AFcU1ZivHwzw2p7lEFUqpNIxvbuuHkEPVjfa0u3 0BbpIwec8myi5OJDArZrCifhDkA96pvhRBNiDAWmXBE8lGEZNYg2GdqSkqiMsWIbAc/o ugpEQWFRIShjeIo68AmJ9TiYmgni2BhJPW550= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=FHJWAsybTkcv8bGvATZVj3Tf5MYkwDCeToqfo7+HHJvTBvOfnMust8aelodH9G8qIT E4cg4psCwzY2tcdMD+5qfL8N6sQ5pJgSdBz3lkfqyAhu90NEHZgN8eyLNxwZAv4mesTS RW2jNv42sfQcYNsuzt4LR0qT4+Tlr8OKmEJeI= Received: by 10.42.133.9 with SMTP id f9mr7564291ict.137.1304976914920; Mon, 09 May 2011 14:35:14 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id ui7sm2549819icb.14.2011.05.09.14.35.14 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 09 May 2011 14:35:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 May 2011 14:34:34 -0700 Message-Id: <1304976889-29675-21-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304976889-29675-1-git-send-email-rth@twiddle.net> References: <1304976889-29675-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.173 Subject: [Qemu-devel] [PATCH 20/35] target-alpha: Disable interrupts properly. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Interrupts are disabled in PALmode, and when the PS IL is high enough. Signed-off-by: Richard Henderson --- cpu-exec.c | 33 ++++++++++++++++++++++++++++++--- target-alpha/cpu.h | 5 +++++ target-alpha/exec.h | 12 +++++++++++- 3 files changed, 46 insertions(+), 4 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 6d43726..fbaa21e 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -525,9 +525,36 @@ int cpu_exec(CPUState *env1) next_tb = 0; } #elif defined(TARGET_ALPHA) - if (interrupt_request & CPU_INTERRUPT_HARD) { - do_interrupt(env); - next_tb = 0; + { + int idx = -1; + /* ??? This hard-codes the OSF/1 interrupt levels. */ + switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { + case 0 ... 3: + if (interrupt_request & CPU_INTERRUPT_HARD) { + idx = EXCP_DEV_INTERRUPT; + } + /* FALLTHRU */ + case 4: + if (interrupt_request & CPU_INTERRUPT_TIMER) { + idx = EXCP_CLK_INTERRUPT; + } + /* FALLTHRU */ + case 5: + if (interrupt_request & CPU_INTERRUPT_SMP) { + idx = EXCP_SMP_INTERRUPT; + } + /* FALLTHRU */ + case 6: + if (interrupt_request & CPU_INTERRUPT_MCHK) { + idx = EXCP_MCHK; + } + } + if (idx >= 0) { + env->exception_index = idx; + env->error_code = 0; + do_interrupt(env); + next_tb = 0; + } } #elif defined(TARGET_CRIS) if (interrupt_request & CPU_INTERRUPT_HARD diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index c1ccf01..b439751 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -316,6 +316,11 @@ enum { EXCP_STQ_C, }; +/* Alpha-specific interrupt pending bits. */ +#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 +#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 +#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 + /* Hardware interrupt (entInt) constants. */ enum { INT_K_IP, diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 6ae96d1..7a325e7 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -39,7 +39,17 @@ register struct CPUAlphaState *env asm(AREG0); static inline int cpu_has_work(CPUState *env) { - return (env->interrupt_request & CPU_INTERRUPT_HARD); + /* Here we are checking to see if the CPU should wake up from HALT. + We will have gotten into this state only for WTINT from PALmode. */ + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU + asleep even if (some) interrupts have been asserted. For now, + assume that if a CPU really wants to stay asleep, it will mask + interrupts at the chipset level, which will prevent these bits + from being set in the first place. */ + return env->interrupt_request & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)