From patchwork Wed May 4 00:59:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 93949 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A4E55B6EFF for ; Wed, 4 May 2011 11:05:07 +1000 (EST) Received: from localhost ([::1]:58870 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQWW-0003na-SH for incoming@patchwork.ozlabs.org; Tue, 03 May 2011 21:05:04 -0400 Received: from eggs.gnu.org ([140.186.70.92]:53083) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQS7-0004kx-Nr for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHQS6-0000lv-Po for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:31 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:37946) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQS6-0000XK-Hz for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:30 -0400 Received: by mail-ey0-f173.google.com with SMTP id 6so222869eyb.4 for ; Tue, 03 May 2011 18:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=nheYuHYCc2zUagme2F+ReTWJTboy/OE4yVOwZfbrlps=; b=dwItp7WSKSanpty2ZPyjQFY+7Y7q8nSJAc/bGWX4Rtqd4OVGUTuUyy0GCgGt2FhLeU Bth4+IyhhUkg+9n9zTKVCs9Ai5ibW6IoPhH6BanVWzK1JelA7JzO8VgLt3oqpe9y5zr/ pCasfrnXV2C6e48Ghky2mHN8YG7JvFTYQiarw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=w3MrAMV2P+PxRRBqRWgEUCEvMqQ+vLmlowOFhetoeHzFNzyoc7RMzk3VX6l8pgB+ys ljUdf2aU6O2n8f0LgZ4vvr3ujBuXrRooMEyA5ol8u+dZoztg7QKU08zRRJiuEkCFUnBO N8p80kU20Nq0ztbtMn+uxpdZE0buPEUB7ccrQ= Received: by 10.213.28.140 with SMTP id m12mr318613ebc.33.1304470830041; Tue, 03 May 2011 18:00:30 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id y7sm438179eeh.14.2011.05.03.18.00.28 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 03 May 2011 18:00:29 -0700 (PDT) Received: by octofox.metropolis (sSMTP sendmail emulation); Wed, 4 May 2011 05:00:27 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 4 May 2011 04:59:13 +0400 Message-Id: <1304470768-16924-13-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.215.173 Cc: Max Filippov Subject: [Qemu-devel] [RFC 13/28] target-xtensa: implement LSAI group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org - base + offset load/store operations for 1/2/4 byte values; - cache operations (not implemented); - multiprocessor synchronization operations. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 1 + target-xtensa/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 0 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a13a6cb..a12db8f 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -107,6 +107,7 @@ enum { enum { SAR = 3, + SCOMPARE1 = 12, }; typedef struct XtensaConfig { diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index a940417..41f3abe 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -58,6 +58,7 @@ static TCGv_i32 cpu_UR[256]; static const char * const sregnames[256] = { [SAR] = "SAR", + [SCOMPARE1] = "SCOMPARE1", }; static const char * const uregnames[256] = { @@ -739,7 +740,94 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 2: /*LSAI*/ +#define gen_load_store(type, shift) do { \ + TCGv_i32 addr = tcg_temp_new_i32(); \ + tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ + tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, 0); \ + tcg_temp_free(addr); \ + } while (0) + + switch (RRI8_R) { + case 0: /*L8UI*/ + gen_load_store(ld8u, 0); + break; + + case 1: /*L16UI*/ + gen_load_store(ld16u, 1); + break; + + case 2: /*L32I*/ + gen_load_store(ld32u, 2); + break; + + case 4: /*S8I*/ + gen_load_store(st8, 0); + break; + + case 5: /*S16I*/ + gen_load_store(st16, 1); + break; + + case 6: /*S32I*/ + gen_load_store(st32, 2); + break; + + case 7: /*CACHEc*/ + break; + + case 9: /*L16SI*/ + gen_load_store(ld16s, 1); + break; + + case 10: /*MOVI*/ + tcg_gen_movi_i32(cpu_R[RRI8_T], + RRI8_IMM8 | (RRI8_S << 8) | + ((RRI8_S & 0x8) ? 0xfffff000 : 0)); + break; + + case 11: /*L32AIy*/ + HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); + gen_load_store(ld32u, 2); /*TODO acquire?*/ + break; + + case 12: /*ADDI*/ + tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); + break; + + case 13: /*ADDMI*/ + tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8); + break; + + case 14: /*S32C1Iy*/ + HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); + { + int label = gen_new_label(); + TCGv_i32 tmp = tcg_temp_local_new_i32(); + TCGv_i32 addr = tcg_temp_local_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); + tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); + tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, 0); + tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_SR[SCOMPARE1], label); + + tcg_gen_qemu_st32(tmp, addr, 0); + + gen_set_label(label); + tcg_temp_free(addr); + tcg_temp_free(tmp); + } + break; + + case 15: /*S32RIy*/ + HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); + gen_load_store(st32, 2); /*TODO release?*/ + break; + + default: /*reserved*/ + break; + } break; +#undef gen_load_store case 3: /*LSCIp*/ HAS_OPTION(XTENSA_OPTION_COPROCESSOR);