From patchwork Sat Apr 30 22:24:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93533 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A396F1007D1 for ; Sun, 1 May 2011 08:27:35 +1000 (EST) Received: from localhost ([::1]:33950 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIdR-00041n-1E for incoming@patchwork.ozlabs.org; Sat, 30 Apr 2011 18:27:33 -0400 Received: from eggs.gnu.org ([140.186.70.92]:49288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIam-0007x7-Sx for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QGIal-0004l0-W7 for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:48 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:42205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIal-0004hP-QS for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:47 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so3274281pzk.4 for ; Sat, 30 Apr 2011 15:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=UYbcqCkMnCydRlmzRlEODZYXZTZGWkh82i4do9u/+CI=; b=mkxMUEJqFMoweyCE8558QjMOfeMxh32bLmS0nyt/JxiMbPDzTiKCEqL1/kHCcRgy0s xl0KSl+0qsKfhIByzgmDs2T4O1X9Fb6emrz88/sCw/D1NlEy84JOc19WtiT6Sya9/VZD Nn/xN9V+v+iWQ83VLyF3xZgwZL5SItnOLzIrg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=fZes1Xf6VkDIp2qyarCFjwfLKkwy7/lFHIncYBGD2MatYY6yb9ISVPc436jJ4xm1wm RrjX+EbeiAHF7GBUm3/vst0rdYsxWO8RN7ix6YNlGvhSd+qwFOHXNYfiqNXObBJQl4hG HNSasLVJKktNAa4Afbl1lt40E8DMuJ6q35gVw= Received: by 10.68.0.72 with SMTP id 8mr7013577pbc.352.1304202287489; Sat, 30 Apr 2011 15:24:47 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id y7sm2797195pbk.30.2011.04.30.15.24.46 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 30 Apr 2011 15:24:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 30 Apr 2011 15:24:31 -0700 Message-Id: <1304202271-24730-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304202271-24730-1-git-send-email-rth@twiddle.net> References: <1304202271-24730-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Cc: Blue Swirl , Aurelien Jarno Subject: [Qemu-devel] [PATCH 8/8] irq: Privatize CPU_INTERRUPT_NMI. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This interrupt name is used by i386, CRIS, and MicroBlaze. Copy the name into each target. Signed-off-by: Richard Henderson --- cpu-all.h | 4 ---- poison.h | 1 - target-cris/cpu.h | 3 +++ target-i386/cpu.h | 1 + target-microblaze/cpu.h | 3 +++ 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 1ecf42b..6a32a75 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -826,10 +826,6 @@ extern CPUState *cpu_single_env; /* First unused bit: 0x2000. */ -/* Temporary remapping from the generic names back to the previous - cpu-specific names. These will be moved to target-foo/cpu.h next. */ -#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 - /* The set of all bits that should be masked when single-stepping. */ #define CPU_INTERRUPT_SSTEP_MASK \ (CPU_INTERRUPT_HARD \ diff --git a/poison.h b/poison.h index 4fcf46d..2b18232 100644 --- a/poison.h +++ b/poison.h @@ -41,7 +41,6 @@ #pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_HALT #pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_NMI #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 diff --git a/target-cris/cpu.h b/target-cris/cpu.h index d908775..16286f7 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -36,6 +36,9 @@ #define EXCP_IRQ 4 #define EXCP_BREAK 5 +/* CRIS-specific interrupt pending bits. */ +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 + /* Register aliases. R0 - R15 */ #define R_FP 8 #define R_SP 14 diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 01880f9..7dedac4 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -468,6 +468,7 @@ /* i386-specific interrupt pending bits. */ #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 536222e..b93e54f 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -41,6 +41,9 @@ struct CPUMBState; #define EXCP_HW_BREAK 5 #define EXCP_HW_EXCP 6 +/* MicroBlaze-specific interrupt pending bits. */ +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 + /* Register aliases. R0 - R15 */ #define R_SP 1 #define SR_PC 0