From patchwork Thu Apr 28 20:51:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B1626B6F62 for ; Fri, 29 Apr 2011 07:01:42 +1000 (EST) Received: from localhost ([::1]:41068 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYLD-0006jt-T6 for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 17:01:39 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48126) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBu-0005uN-Gf for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:52:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBt-0005iS-Gv for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:52:02 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBt-0005Xk-7v for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:52:01 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so2296231pzk.4 for ; Thu, 28 Apr 2011 13:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=NBnjcliMT8ITd9j6o7tgZmx0zUekL4XDYs4Y8wmM9W0=; b=hzu6uQoiUZAzMpxsdP+3goSMrrngiTx5dB7d25yktD2kfIoyNcO9u0LlSu1aV8oG4b sQsxrCfQCvx3oNovFkojACf9qDIhJmHLYMwBS/10DqMSb54/eudMVcSlxSfuyWNk2i8N dDEFQ6T7kpPe16XDSJHAgTw3rvsvw8zOgQZyE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=LXY5B2ydYdxJjGMoqkV62THC+kWoimral5SCqT3iMDCI9vgIU51FDi2pk+G3rl7Z5a Y5EFv8G4ADM4Txq2pljqpLmUQ31a+WkTtCwsWKC1P5FVXKAcJREY51diIvGioIitwUvM lqQdynKdL7bKnOJJnDFDlQGVdiLJD3cIEG0Ms= Received: by 10.142.62.9 with SMTP id k9mr1402379wfa.162.1304023920781; Thu, 28 Apr 2011 13:52:00 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.59 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:52:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:51:15 -0700 Message-Id: <1304023875-25040-34-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH 33/33] target-alpha: Add high-resolution access to wall clock and an alarm. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The alarm is a fully general one-shot time comparator, which will be usable under Linux as a hrtimer source. It's much more flexible than the RTC source available on real hardware. The wall clock allows the guest access to the host timekeeping. Much like the KVM wall clock source for other guests. Both are accessed via the PALcode Cserve entry point. Signed-off-by: Richard Henderson --- hw/alpha_typhoon.c | 22 ++++++++++++++++++++-- target-alpha/cpu.h | 4 ++++ target-alpha/helper.h | 4 ++++ target-alpha/op_helper.c | 15 +++++++++++++++ target-alpha/translate.c | 14 ++++++++++++++ 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index fb47481..d7b878c 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -676,6 +676,16 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) } } +static void typhoon_alarm_timer(void *opaque) +{ + TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3); + int cpu = (uintptr_t)opaque & 3; + + /* Set the ITI bit for this cpu. */ + s->cchip.misc |= 1 << (cpu + 4); + cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER); +} + PCIBus *typhoon_init(qemu_irq *p_isa_irq, qemu_irq *p_rtc_irq, CPUState *cpus[3], pci_map_irq_fn sys_map_irq) { @@ -685,14 +695,22 @@ PCIBus *typhoon_init(qemu_irq *p_isa_irq, qemu_irq *p_rtc_irq, TyphoonState *s; PCIBus *b; qemu_irq *irqs; - int region; + int i, region; dev = qdev_create(NULL, "typhoon-pcihost"); p = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); s = container_of(p, TyphoonState, host); /* Remember the CPUs so that we can deliver interrupts to them. */ - memcpy(s->cchip.cpu, cpus, 4 * sizeof(CPUState *)); + for (i = 0; i < 4; i++) { + CPUState *env = cpus[i]; + s->cchip.cpu[i] = env; + if (env) { + env->alarm_timer = qemu_new_timer_ns(rtc_clock, + typhoon_alarm_timer, + (void *)((uintptr_t)s + i)); + } + } irqs = qemu_allocate_irqs(typhoon_set_irq, s, 64); *p_isa_irq = irqs[55]; diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 30ecf2d..b974cc3 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -266,6 +266,10 @@ struct CPUAlphaState { uint64_t shadow[8]; uint64_t scratch[24]; + /* This alarm doesn't exist in real hardware; we wish it did. */ + struct QEMUTimer *alarm_timer; + uint64_t alarm_expire; + #if TARGET_LONG_BITS > HOST_LONG_BITS /* temporary fixed-point registers * used to emulate 64 bits target on 32 bits hosts diff --git a/target-alpha/helper.h b/target-alpha/helper.h index c352c24..b693cee 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -113,7 +113,11 @@ DEF_HELPER_2(stq_c_phys, i64, i64, i64) DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) + DEF_HELPER_1(halt, void, i64); + +DEF_HELPER_FLAGS_0(get_time, TCG_CALL_CONST, i64) +DEF_HELPER_FLAGS_1(set_alarm, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 80656f5..c37fb5f 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1225,6 +1225,21 @@ void helper_halt(uint64_t restart) qemu_system_shutdown_request(); } } + +uint64_t helper_get_time(void) +{ + return qemu_get_clock_ns(rtc_clock); +} + +void helper_set_alarm(uint64_t expire) +{ + if (expire) { + env->alarm_expire = expire; + qemu_mod_timer(env->alarm_timer, expire); + } else { + qemu_del_timer(env->alarm_timer); + } +} #endif /*****************************************************************************/ diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 9edcd74..f34c53e 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1594,6 +1594,9 @@ static int cpu_pr_data(int pr) return offsetof(CPUAlphaState, shadow[pr - 32]); case 40 ... 63: return offsetof(CPUAlphaState, scratch[pr - 40]); + + case 251: + return offsetof(CPUAlphaState, alarm_expire); } return 0; } @@ -1608,6 +1611,12 @@ static void gen_mfpr(int ra, int regno) return; } + if (regno == 250) { + /* WALL_TIME */ + gen_helper_get_time(cpu_ir[ra]); + return; + } + /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ if (data == 0) { @@ -1654,6 +1663,11 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) gen_helper_halt(tmp); return EXIT_PC_STALE; + case 251: + /* ALARM */ + gen_helper_set_alarm(tmp); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */