From patchwork Thu Apr 28 20:51:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E0AB2B6FBC for ; Fri, 29 Apr 2011 06:59:44 +1000 (EST) Received: from localhost ([::1]:34074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYJJ-0003F5-0D for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 16:59:41 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBo-0005hz-1F for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBn-0005hA-4l for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:55 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBm-0005Xk-W1 for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:55 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so2296231pzk.4 for ; Thu, 28 Apr 2011 13:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=vEDqgIHLLfAZ9M6GmjiC+0i7zpIR5t5rLUhtY9yCwTg=; b=MQYLo4GctwzQ2Otw8rXiEDclW7TA7NJ8WOxJeUNIBBOXmHf2KgzjOYMEgUQFeRky+L pV3QYkJKAJRIY+CfzORgS6DAXeBn6kpCqjoIP6ufWubXBgebE5VE3jqGvXdc+XHB2Z4W hKnyxq3NzkBjklCEK3Ldwyd5j4aM8Rlh8raTw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=mzZDtLLJyOU77uNoBJN32HieL3lUpYHmxh5lztfR+LcpUkedsHHXN6IpQ9VxXp77Is IVk6ubzRxqyFiCsCGZ22S9YGyhHvlH/FiP3CyuFwyXTPIilCVpXujmcAXOhM6DZOxnyF M40EKxmRKqq51WrnP3DGMQcuqUOSgAVlN582s= Received: by 10.143.154.36 with SMTP id g36mr1315636wfo.278.1304023914507; Thu, 28 Apr 2011 13:51:54 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.53 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:51:10 -0700 Message-Id: <1304023875-25040-29-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH 28/33] target-alpha: Implement TLB flush primitives. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Expose these via MTPR, more or less like the real HW does. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 3 +++ target-alpha/op_helper.c | 11 ++++++++++- target-alpha/translate.c | 32 +++++++++++++++++++++----------- 3 files changed, 34 insertions(+), 12 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 9ffc372..2dec57e 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -110,6 +110,9 @@ DEF_HELPER_2(stl_phys, void, i64, i64) DEF_HELPER_2(stq_phys, void, i64, i64) DEF_HELPER_2(stl_c_phys, i64, i64, i64) DEF_HELPER_2(stq_c_phys, i64, i64, i64) + +DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) +DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 36b8289..d332719 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1205,6 +1205,16 @@ void helper_hw_ret (uint64_t a) swap_shadow_regs(env); } } + +void helper_tbia(void) +{ + tlb_flush(env, 1); +} + +void helper_tbis(uint64_t p) +{ + tlb_flush_page(env, p); +} #endif /*****************************************************************************/ @@ -1335,5 +1345,4 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) } env = saved_env; } - #endif diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 8b9dded..8107d19 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1624,7 +1624,6 @@ static void gen_mfpr(int ra, int regno) static void gen_mtpr(int rb, int regno) { TCGv tmp; - int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1632,16 +1631,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* The basic registers are data only, and unknown registers - are read-zero, write-ignore. */ - data = cpu_pr_data(regno); - if (data != 0) { - if (data & PR_BYTE) { - tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); - } else if (data & PR_LONG) { - tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); - } else { - tcg_gen_st_i64(tmp, cpu_env, data); + /* These two register numbers perform a TLB cache flush. Thankfully we + can only do this inside PALmode, which means that the current basic + block cannot be affected by the change in mappings. */ + if (regno == 255) { + /* TBIA */ + gen_helper_tbia(); + } else if (regno == 254) { + /* TBIS */ + gen_helper_tbis(tmp); + } else { + /* The basic registers are data only, and unknown registers + are read-zero, write-ignore. */ + int data = cpu_pr_data(regno); + if (data != 0) { + if (data & PR_BYTE) { + tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); + } else if (data & PR_LONG) { + tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); + } else { + tcg_gen_st_i64(tmp, cpu_env, data); + } } }