From patchwork Thu Apr 28 20:51:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B69E2B6FB9 for ; Fri, 29 Apr 2011 06:58:53 +1000 (EST) Received: from localhost ([::1]:50004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYIV-0001jP-4B for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 16:58:51 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48022) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBl-0005cq-Aq for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBk-0005g6-7r for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:53 -0400 Received: from mail-pv0-f173.google.com ([74.125.83.173]:64385) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBk-0005Zh-0R for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:52 -0400 Received: by mail-pv0-f173.google.com with SMTP id 3so2495040pvg.4 for ; Thu, 28 Apr 2011 13:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=//xlXHU5lAaZdGIwUWCg8s4g8PrixwbxWjqUEo7lyjo=; b=TsxiF+kvFetbml9LmEjWLrUt7osRJQp91dFr1/wmjBSU2HPQEIkT2mIcsOk+Zn1Lmn OPJzNPtvG6ssxnkuqVpxl9xCynFm0EiBUUw3WLENVazVqdxJek/AWTLe1b2oA4CP4azf g2BHzxX9uK4ZgnPLeP6Ip2cPwnStrcaiL9mds= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=tp01sl+C8whk6ANew9ooZbIluYdW5NJ7FGGJYttTvTiZqyT2D928BN6grNXZ2wscwA jIq2pV5LRz6D772jh+vnwJvyd5w6Xx3DHRvax2Q9fHsjeGK2o9nhUz3QikIZT07VwlPw Vhn3cTCsJWMfrfMY1nSm/IWqYgOPD2ygmCKdE= Received: by 10.142.55.16 with SMTP id d16mr1410072wfa.27.1304023911497; Thu, 28 Apr 2011 13:51:51 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.50 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:51:07 -0700 Message-Id: <1304023875-25040-26-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.83.173 Subject: [Qemu-devel] [PATCH 25/33] target-alpha: Trap for unassigned and unaligned addresses. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- exec-all.h | 2 +- exec.c | 12 ++++++------ target-alpha/cpu.h | 6 +++++- target-alpha/op_helper.c | 26 ++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 8 deletions(-) diff --git a/exec-all.h b/exec-all.h index 7c2d29f..6d3ae77 100644 --- a/exec-all.h +++ b/exec-all.h @@ -322,7 +322,7 @@ static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong add } pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { -#if defined(TARGET_SPARC) || defined(TARGET_MIPS) +#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) do_unassigned_access(addr, 0, 1, 0, 4); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); diff --git a/exec.c b/exec.c index c82ff70..c8b053f 100644 --- a/exec.c +++ b/exec.c @@ -3094,7 +3094,7 @@ uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 0, 0, 0, 1); #endif return 0; @@ -3105,7 +3105,7 @@ uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 0, 0, 0, 2); #endif return 0; @@ -3116,7 +3116,7 @@ uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 0, 0, 0, 4); #endif return 0; @@ -3127,7 +3127,7 @@ void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 1, 0, 0, 1); #endif } @@ -3137,7 +3137,7 @@ void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 1, 0, 0, 2); #endif } @@ -3147,7 +3147,7 @@ void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 1, 0, 0, 4); #endif } diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index bb76edb..59b3bc3 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -429,7 +429,11 @@ void do_interrupt (CPUState *env); uint64_t cpu_alpha_load_fpcr (CPUState *env); void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); -extern void swap_shadow_regs(CPUState *env); +#ifndef CONFIG_USER_ONLY +void swap_shadow_regs(CPUState *env); +extern QEMU_NORETURN void do_unassigned_access(target_phys_addr_t addr, + int, int, int, int); +#endif /* Bits in TB->FLAGS that control how translation is processed. */ enum { diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 03b5091..91ef90a 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1265,7 +1265,33 @@ uint64_t helper_stq_c_phys(uint64_t p, uint64_t v) return ret; } +static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, + int is_user, void *retaddr) +{ + uint64_t pc; + uint32_t insn; + + do_restore_state(retaddr); + + pc = env->pc; + insn = ldl_code(pc); + + env->trap_arg0 = addr; + env->trap_arg1 = insn >> 26; /* opcode */ + env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ + helper_excp(EXCP_UNALIGN, 0); +} + +void QEMU_NORETURN do_unassigned_access(target_phys_addr_t addr, int is_write, + int is_exec, int unused, int size) +{ + env->trap_arg0 = addr; + env->trap_arg1 = is_write; + dynamic_excp(EXCP_MCHK, 0); +} + #define MMUSUFFIX _mmu +#define ALIGNED_ONLY #define SHIFT 0 #include "softmmu_template.h"