From patchwork Thu Apr 28 20:50:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2BB20100A08 for ; Fri, 29 Apr 2011 06:56:20 +1000 (EST) Received: from localhost ([::1]:41390 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYG1-0005OH-GF for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 16:56:17 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBe-0005QD-1p for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBc-0005dl-7x for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:45 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBb-0005Xk-Sc for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:44 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so2296231pzk.4 for ; Thu, 28 Apr 2011 13:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=Yg+MTcjfkTvc9dv615AQ73gh4WPqjA4mEyEixlrWvoM=; b=PCeI2/EOdipeUcsApDKlqO929GTd1kq/eEjfVqDYzh0hbm4/D9wgdiJP0G+nOX+2jj 6z3xboo+3FY4wi6Lw6AO7u/gIbrZ3Sf9njVqXF+HpZNn5BS2/CVbIXNkXCbgqFqnR78W 5vabllOdh+TRXWraGTJssNzskt0cPrmONLez8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=fPs5aBag4cOQEArccCPyMB0B6jgBByJtrgEzxEBfkG0e1/ZxhvssMYMqcwlodQtX5m rWoeoHUlYSbhDnG1XSQO9g98kRQUGbjIaWhcBN0SOkaTidzTGRQxcR8QamtoxdPSRelo 1PxztxQLRfmUE6CJtN6VG8St3pT+EjHEXObO8= Received: by 10.143.26.6 with SMTP id d6mr1314864wfj.290.1304023903404; Thu, 28 Apr 2011 13:51:43 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.42 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:50:59 -0700 Message-Id: <1304023875-25040-18-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH 17/33] target-alpha: Swap shadow registers moving to/from PALmode. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 1 + target-alpha/helper.c | 37 ++++++++++++++++++++++++++++++++++++- target-alpha/op_helper.c | 5 ++++- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 60445dc..7e4c46f 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -381,6 +381,7 @@ void do_interrupt (CPUState *env); uint64_t cpu_alpha_load_fpcr (CPUState *env); void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); +extern void swap_shadow_regs(CPUState *env); static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) diff --git a/target-alpha/helper.c b/target-alpha/helper.c index a49f632..4f706f2 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -168,6 +168,38 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return 1; } #else +void swap_shadow_regs(CPUState *env) +{ + uint64_t i0, i1, i2, i3, i4, i5, i6, i7; + + i0 = env->ir[8]; + i1 = env->ir[9]; + i2 = env->ir[10]; + i3 = env->ir[11]; + i4 = env->ir[12]; + i5 = env->ir[13]; + i6 = env->ir[14]; + i7 = env->ir[25]; + + env->ir[8] = env->shadow[0]; + env->ir[9] = env->shadow[1]; + env->ir[10] = env->shadow[2]; + env->ir[11] = env->shadow[3]; + env->ir[12] = env->shadow[4]; + env->ir[13] = env->shadow[5]; + env->ir[14] = env->shadow[6]; + env->ir[25] = env->shadow[7]; + + env->shadow[0] = i0; + env->shadow[1] = i1; + env->shadow[2] = i2; + env->shadow[3] = i3; + env->shadow[4] = i4; + env->shadow[5] = i5; + env->shadow[6] = i6; + env->shadow[7] = i7; +} + target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { return -1; @@ -290,7 +322,10 @@ void do_interrupt (CPUState *env) env->pc = env->palbr + i; /* Switch to PALmode. */ - env->pal_mode = 1; + if (!env->pal_mode) { + env->pal_mode = 1; + swap_shadow_regs(env); + } #endif /* !USER_ONLY */ } diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index fc5020a..03b5091 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1189,9 +1189,12 @@ uint64_t helper_cvtqg (uint64_t a) void helper_hw_ret (uint64_t a) { env->pc = a & ~3; - env->pal_mode = a & 1; env->intr_flag = 0; env->lock_addr = -1; + if ((a & 1) == 0) { + env->pal_mode = 0; + swap_shadow_regs(env); + } } #endif