From patchwork Thu Apr 28 20:50:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3309A1007D7 for ; Fri, 29 Apr 2011 06:54:57 +1000 (EST) Received: from localhost ([::1]:37060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYEg-0002aQ-9z for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 16:54:54 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47773) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBV-00059o-5l for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBU-0005ai-65 for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:37 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBU-0005Xk-1Z for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:36 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so2296231pzk.4 for ; Thu, 28 Apr 2011 13:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=RYwcOFDjhrhZWewxDi2SDg+thxe2TlI649+aSRrZU8Q=; b=GQKUTVBDU4gCdAz90ZnwDTi2nmdVtBXSsc57pAwzL7SCyYF2gLZ9dDwE9hf7SbHFQj OmEzTxlyumeMcw9FAfey4vcj384kLs6l0HRRQoV+82mJ9vUxh/0qOQkXH0X9gxkYCQnO kQx6hzgaz8IbYsPKGBm8CYgwgFeriF0lzmFio= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=reCVtgAsA9D7CNVKsmsLSXURRcMrzK607zK+NJQxRaDJmLYqPnmeINEo/Py1pqD2Dm wrnjrfFlPce+hgtW06VJuuksVlxUo1NaznwZQdzWDuuTYorNXrEMzs5aRN4Ghrhx318V SKMMsaaYI7k2A5sz6gxGKztGDxGoT6zB07nNg= Received: by 10.142.204.1 with SMTP id b1mr1311429wfg.194.1304023895607; Thu, 28 Apr 2011 13:51:35 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.34 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:50:52 -0700 Message-Id: <1304023875-25040-11-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH 10/33] target-alpha: Cleanup MMU modes. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Don't bother including executive and supervisor modes. Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 36 ++++++++++++++++++++++++++++-------- 1 files changed, 28 insertions(+), 8 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 1fc21dc..bdd396c 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -192,6 +192,33 @@ enum { #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) +/* MMU modes definitions */ + +/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user. + The Unix PALcode only exposes the kernel and user modes; presumably + executive and supervisor are used by VMS. + + PALcode itself uses physical mode for code and kernel mode for data; + there are PALmode instructions that can access data via physical mode + or via an os-installed "alternate mode", which is one of the 4 above. + + QEMU does not currently properly distinguish between code/data when + looking up addresses. To avoid having to address this issue, our + emulated PALcode will cheat and use the KSEG mapping for its code+data + rather than physical addresses. + + Moreover, we're only emulating Unix PALcode, and not attempting VMS. + + All of which allows us to drop all but kernel and user modes. + Elide the unused MMU modes to save space. */ + +#define NB_MMU_MODES 2 + +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _user +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 1 + typedef struct CPUAlphaState CPUAlphaState; struct CPUAlphaState { @@ -246,16 +273,9 @@ struct CPUAlphaState { #define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler -/* MMU modes definitions */ -#define NB_MMU_MODES 4 -#define MMU_MODE0_SUFFIX _kernel -#define MMU_MODE1_SUFFIX _executive -#define MMU_MODE2_SUFFIX _supervisor -#define MMU_MODE3_SUFFIX _user -#define MMU_USER_IDX 3 static inline int cpu_mmu_index (CPUState *env) { - return (env->ps >> 3) & 3; + return (env->ps >> 3) & 1; } #include "cpu-all.h"