From patchwork Tue Apr 19 15:04:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 91999 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F24D7B6F94 for ; Wed, 20 Apr 2011 01:42:11 +1000 (EST) Received: from localhost ([::1]:50708 helo=lists2.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCD45-0002eE-E4 for incoming@patchwork.ozlabs.org; Tue, 19 Apr 2011 11:42:09 -0400 Received: from eggs.gnu.org ([140.186.70.92]:53483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCD3g-0002b2-1Z for qemu-devel@nongnu.org; Tue, 19 Apr 2011 11:41:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QCD3e-0005JO-OO for qemu-devel@nongnu.org; Tue, 19 Apr 2011 11:41:44 -0400 Received: from a.mail.sonic.net ([64.142.16.245]:56255) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCD3e-0005Fh-Ci for qemu-devel@nongnu.org; Tue, 19 Apr 2011 11:41:42 -0400 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by a.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p3JF5A12030907 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 19 Apr 2011 08:05:10 -0700 Received: from are.twiddle.net (localhost [127.0.0.1]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p3JF5AbG012900 for ; Tue, 19 Apr 2011 08:05:10 -0700 Received: (from rth@localhost) by are.twiddle.net (8.14.4/8.14.4/Submit) id p3JF5AG3012899 for qemu-devel@nongnu.org; Tue, 19 Apr 2011 08:05:10 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Apr 2011 08:04:59 -0700 Message-Id: <1303225501-12778-23-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1303225501-12778-1-git-send-email-rth@twiddle.net> References: <1303225501-12778-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 64.142.16.245 Subject: [Qemu-devel] [PATCH 22/24] target-alpha: Implement TLB flush primitives. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Expose these via MTPR, more or less like the real HW does. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 3 +++ target-alpha/op_helper.c | 11 ++++++++++- target-alpha/translate.c | 32 +++++++++++++++++++++----------- 3 files changed, 34 insertions(+), 12 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 9ffc372..2dec57e 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -110,6 +110,9 @@ DEF_HELPER_2(stl_phys, void, i64, i64) DEF_HELPER_2(stq_phys, void, i64, i64) DEF_HELPER_2(stl_c_phys, i64, i64, i64) DEF_HELPER_2(stq_c_phys, i64, i64, i64) + +DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) +DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 5902cd6..718f87d 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1174,6 +1174,16 @@ void helper_hw_ret (uint64_t a) swap_shadow_regs(env); } } + +void helper_tbia(void) +{ + tlb_flush(env, 1); +} + +void helper_tbis(uint64_t p) +{ + tlb_flush_page(env, p); +} #endif /*****************************************************************************/ @@ -1326,5 +1336,4 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) } env = saved_env; } - #endif diff --git a/target-alpha/translate.c b/target-alpha/translate.c index c2db1ae..fa0cb09 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1620,7 +1620,6 @@ static void gen_mfpr(int ra, int regno) static void gen_mtpr(int rb, int regno) { TCGv tmp; - int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1628,16 +1627,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* The basic registers are data only, and unknown registers - are read-zero, write-ignore. */ - data = cpu_pr_data(regno); - if (data != 0) { - if (data & PR_BYTE) { - tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); - } else if (data & PR_LONG) { - tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); - } else { - tcg_gen_st_i64(tmp, cpu_env, data); + /* These two register numbers perform a TLB cache flush. Thankfully we + can only do this inside PALmode, which means that the current basic + block cannot be affected by the change in mappings. */ + if (regno == 255) { + /* TBIA */ + gen_helper_tbia(); + } else if (regno == 254) { + /* TBIS */ + gen_helper_tbis(tmp); + } else { + /* The basic registers are data only, and unknown registers + are read-zero, write-ignore. */ + int data = cpu_pr_data(regno); + if (data != 0) { + if (data & PR_BYTE) { + tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); + } else if (data & PR_LONG) { + tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); + } else { + tcg_gen_st_i64(tmp, cpu_env, data); + } } }