From patchwork Tue Apr 19 15:04:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 92027 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BA660B7014 for ; Wed, 20 Apr 2011 02:15:01 +1000 (EST) Received: from localhost ([::1]:45857 helo=lists2.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCDZr-0007m8-6i for incoming@patchwork.ozlabs.org; Tue, 19 Apr 2011 12:14:59 -0400 Received: from eggs.gnu.org ([140.186.70.92]:44736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCDWN-0001o3-OV for qemu-devel@nongnu.org; Tue, 19 Apr 2011 12:11:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QCDWH-00037D-71 for qemu-devel@nongnu.org; Tue, 19 Apr 2011 12:11:23 -0400 Received: from b.mail.sonic.net ([64.142.19.5]:46572) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCDWG-00036c-Uh for qemu-devel@nongnu.org; Tue, 19 Apr 2011 12:11:17 -0400 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by b.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p3JF5AHw008139 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 19 Apr 2011 08:05:10 -0700 Received: from are.twiddle.net (localhost [127.0.0.1]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p3JF59PA012892 for ; Tue, 19 Apr 2011 08:05:09 -0700 Received: (from rth@localhost) by are.twiddle.net (8.14.4/8.14.4/Submit) id p3JF597q012891 for qemu-devel@nongnu.org; Tue, 19 Apr 2011 08:05:09 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Apr 2011 08:04:57 -0700 Message-Id: <1303225501-12778-21-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1303225501-12778-1-git-send-email-rth@twiddle.net> References: <1303225501-12778-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 64.142.19.5 Subject: [Qemu-devel] [PATCH 20/24] target-alpha: Trap for unassigned and unaligned addresses. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- exec-all.h | 2 +- exec.c | 12 ++++++------ target-alpha/cpu.h | 6 +++++- target-alpha/op_helper.c | 39 ++++++++++++++++++++++++++++++++++++++- 4 files changed, 50 insertions(+), 9 deletions(-) diff --git a/exec-all.h b/exec-all.h index 496c001..e525662 100644 --- a/exec-all.h +++ b/exec-all.h @@ -323,7 +323,7 @@ static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong add } pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { -#if defined(TARGET_SPARC) || defined(TARGET_MIPS) +#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) do_unassigned_access(addr, 0, 1, 0, 4); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); diff --git a/exec.c b/exec.c index 994d51b..c3c2809 100644 --- a/exec.c +++ b/exec.c @@ -3095,7 +3095,7 @@ uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 0, 0, 0, 1); #endif return 0; @@ -3106,7 +3106,7 @@ uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 0, 0, 0, 2); #endif return 0; @@ -3117,7 +3117,7 @@ uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 0, 0, 0, 4); #endif return 0; @@ -3128,7 +3128,7 @@ void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 1, 0, 0, 1); #endif } @@ -3138,7 +3138,7 @@ void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 1, 0, 0, 2); #endif } @@ -3148,7 +3148,7 @@ void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif -#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) +#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) do_unassigned_access(addr, 1, 0, 0, 4); #endif } diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index d133cc6..f64dcd1 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -422,7 +422,11 @@ void do_interrupt (CPUState *env); uint64_t cpu_alpha_load_fpcr (CPUState *env); void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); -extern void swap_shadow_regs(CPUState *env); +#ifndef CONFIG_USER_ONLY +void swap_shadow_regs(CPUState *env); +extern QEMU_NORETURN void do_unassigned_access(target_phys_addr_t addr, + int, int, int, int); +#endif /* Bits in TB->FLAGS that control how translation is processed. */ enum { diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index d502bca..cc8a33d 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1242,7 +1242,44 @@ uint64_t helper_stq_c_phys(uint64_t p, uint64_t v) return ret; } +static void do_restore_state(void *pc_ptr) +{ + TranslationBlock *tb; + unsigned long pc = (unsigned long) pc_ptr; + + tb = tb_find_pc(pc); + if (tb) { + cpu_restore_state(tb, env, pc, NULL); + } +} + +static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, + int is_user, void *retaddr) +{ + uint64_t pc; + uint32_t insn; + + do_restore_state(retaddr); + + pc = env->pc; + insn = ldl_code(pc); + + env->trap_arg0 = addr; + env->trap_arg1 = insn >> 26; /* opcode */ + env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ + helper_excp(EXCP_UNALIGN, 0); +} + +void QEMU_NORETURN do_unassigned_access(target_phys_addr_t addr, int is_write, + int is_exec, int unused, int size) +{ + env->trap_arg0 = addr; + env->trap_arg1 = is_write; + helper_excp(EXCP_MCHK, 0); +} + #define MMUSUFFIX _mmu +#define ALIGNED_ONLY #define SHIFT 0 #include "softmmu_template.h" @@ -1272,7 +1309,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) saved_env = env; env = cpu_single_env; ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); - if (!likely(ret == 0)) { + if (unlikely(ret != 0)) { if (likely(retaddr)) { /* now we have a real cpu fault */ pc = (unsigned long)retaddr;