From patchwork Tue Apr 19 15:04:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 92017 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 95CB6B6F06 for ; Wed, 20 Apr 2011 02:11:50 +1000 (EST) Received: from localhost ([::1]:35044 helo=lists2.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCDWl-0001mX-Gx for incoming@patchwork.ozlabs.org; Tue, 19 Apr 2011 12:11:47 -0400 Received: from eggs.gnu.org ([140.186.70.92]:44646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCDWJ-0001ky-4B for qemu-devel@nongnu.org; Tue, 19 Apr 2011 12:11:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QCDWG-00036F-LV for qemu-devel@nongnu.org; Tue, 19 Apr 2011 12:11:19 -0400 Received: from b.mail.sonic.net ([64.142.19.5]:46553) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCDWG-00035e-Az for qemu-devel@nongnu.org; Tue, 19 Apr 2011 12:11:16 -0400 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by b.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p3JF58W8008125 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 19 Apr 2011 08:05:08 -0700 Received: from are.twiddle.net (localhost [127.0.0.1]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p3JF58vM012876 for ; Tue, 19 Apr 2011 08:05:08 -0700 Received: (from rth@localhost) by are.twiddle.net (8.14.4/8.14.4/Submit) id p3JF58nh012875 for qemu-devel@nongnu.org; Tue, 19 Apr 2011 08:05:08 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Apr 2011 08:04:53 -0700 Message-Id: <1303225501-12778-17-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1303225501-12778-1-git-send-email-rth@twiddle.net> References: <1303225501-12778-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 64.142.19.5 Subject: [Qemu-devel] [PATCH 16/24] target-alpha: Disable interrupts properly. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Interrupts are disabled in PALmode, and when the PS IL is high enough. We don't actually get the interrupt levels correct yet; settle for interrupts enabled only at IL0. Signed-off-by: Richard Henderson --- cpu-exec.c | 16 +++++++++++++--- target-alpha/exec.h | 7 ++++++- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 5d6c9a8..68c3d1d 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -529,9 +529,19 @@ int cpu_exec(CPUState *env1) next_tb = 0; } #elif defined(TARGET_ALPHA) - if (interrupt_request & CPU_INTERRUPT_HARD) { - do_interrupt(env); - next_tb = 0; + if (env->pal_mode == 0 && (env->ps & PS_INT_MASK) == 0) { + int idx = -1; + if (interrupt_request & CPU_INTERRUPT_HARD) { + idx = EXCP_DEV_INTERRUPT; + } + if (interrupt_request & CPU_INTERRUPT_TIMER) { + idx = EXCP_CLK_INTERRUPT; + } + if (idx >= 0) { + env->exception_index = idx; + do_interrupt(env); + next_tb = 0; + } } #elif defined(TARGET_CRIS) if (interrupt_request & CPU_INTERRUPT_HARD diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 6ae96d1..a504758 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -39,7 +39,12 @@ register struct CPUAlphaState *env asm(AREG0); static inline int cpu_has_work(CPUState *env) { - return (env->interrupt_request & CPU_INTERRUPT_HARD); + /* ??? There's a model-specific mapping between external hardware + interrupt numbers and the Unix PALcode interrupt levels. */ + int req = CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER; + return ((env->interrupt_request & req) + && env->pal_mode == 0 + && (env->ps & PS_INT_MASK) == 0); } static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)