From patchwork Tue Feb 15 13:44:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 83248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 52378B711B for ; Wed, 16 Feb 2011 00:46:32 +1100 (EST) Received: from localhost ([127.0.0.1]:47742 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PpLEb-0005nS-GD for incoming@patchwork.ozlabs.org; Tue, 15 Feb 2011 08:46:29 -0500 Received: from [140.186.70.92] (port=41036 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PpLDC-0005lU-V6 for qemu-devel@nongnu.org; Tue, 15 Feb 2011 08:45:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PpLD9-0005KX-Lu for qemu-devel@nongnu.org; Tue, 15 Feb 2011 08:45:02 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:56889) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PpLD9-0005J7-7o for qemu-devel@nongnu.org; Tue, 15 Feb 2011 08:44:59 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1PpLD0-0001Oc-JK; Tue, 15 Feb 2011 13:44:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 15 Feb 2011 13:44:50 +0000 Message-Id: <1297777490-5323-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297777490-5323-1-git-send-email-peter.maydell@linaro.org> References: <1297777490-5323-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Christophe Lyon , patches@linaro.org Subject: [Qemu-devel] [PATCH 10/10] target-arm: Fix shift by immediate and narrow where src, dest overlap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For Neon shifts by immediate and narrow, correctly handle the case where the source registers and the destination registers overlap (the second pass should use the original register contents, not the results of the first pass). Signed-off-by: Peter Maydell --- target-arm/translate.c | 38 +++++++++++++++++++++++++++----------- 1 files changed, 27 insertions(+), 11 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index a02b20f..4d5d305 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4839,31 +4839,47 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) abort(); } + if (size == 3) { + neon_load_reg64(cpu_V0, rm); + neon_load_reg64(cpu_V1, rm + 1); + } else { + tmp4 = neon_load_reg(rm + 1, 0); + tmp5 = neon_load_reg(rm + 1, 1); + } for (pass = 0; pass < 2; pass++) { if (size == 3) { - neon_load_reg64(cpu_V0, rm + pass); + TCGv_i64 in; + if (pass == 0) { + in = cpu_V0; + } else { + in = cpu_V1; + } if (q) { if (input_unsigned) { - gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_rshl_u64(cpu_V0, in, tmp64); } else { - gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_rshl_s64(cpu_V0, in, tmp64); } } else { if (input_unsigned) { - gen_helper_neon_shl_u64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_shl_u64(cpu_V0, in, tmp64); } else { - gen_helper_neon_shl_s64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_shl_s64(cpu_V0, in, tmp64); } } } else { - tmp = neon_load_reg(rm + pass, 0); + if (pass == 0) { + tmp = neon_load_reg(rm, 0); + } else { + tmp = tmp4; + } gen_neon_shift_narrow(size, tmp, tmp2, q, input_unsigned); - tmp3 = neon_load_reg(rm + pass, 1); + if (pass == 0) { + tmp3 = neon_load_reg(rm, 1); + } else { + tmp3 = tmp5; + } gen_neon_shift_narrow(size, tmp3, tmp2, q, input_unsigned); tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);