From patchwork Wed Feb 9 13:48:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 82462 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 63E74B70E3 for ; Thu, 10 Feb 2011 00:51:51 +1100 (EST) Received: from localhost ([127.0.0.1]:43511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PnASR-0002Hv-Mm for incoming@patchwork.ozlabs.org; Wed, 09 Feb 2011 08:51:47 -0500 Received: from [140.186.70.92] (port=58352 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PnAPB-0000tv-DX for qemu-devel@nongnu.org; Wed, 09 Feb 2011 08:48:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PnAP9-0004ed-E8 for qemu-devel@nongnu.org; Wed, 09 Feb 2011 08:48:25 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:51013) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PnAP8-0004b4-SO for qemu-devel@nongnu.org; Wed, 09 Feb 2011 08:48:23 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PnAOy-0001JU-Og; Wed, 09 Feb 2011 13:48:12 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 9 Feb 2011 13:48:07 +0000 Message-Id: <1297259292-5025-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297259292-5025-1-git-send-email-peter.maydell@linaro.org> References: <1297259292-5025-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Christophe Lyon , patches@linaro.org Subject: [Qemu-devel] [PATCH 1/6] softfloat: Add float16 type and float16 NaN handling functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a float16 type to softfloat, rather than using bits16 directly. Also add the missing functions float16_is_quiet_nan(), float16_is_signaling_nan() and float16_maybe_silence_nan(), which are needed for the float16 conversion routines. Signed-off-by: Peter Maydell --- fpu/softfloat-specialize.h | 59 ++++++++++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 8 +++--- fpu/softfloat.h | 12 +++++++- 3 files changed, 73 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index eb644b2..bc9a66c 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -57,6 +57,65 @@ typedef struct { } commonNaNT; /*---------------------------------------------------------------------------- +| The pattern for a default generated half-precision NaN. +*----------------------------------------------------------------------------*/ +#if defined(TARGET_ARM) +#define float16_default_nan 0x7E00 +#elif SNAN_BIT_IS_ONE +#define float16_default_nan 0x7DFF +#else +#define float16_default_nan 0xFE00 +#endif + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is a quiet +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +int float16_is_quiet_nan(float16 a) +{ +#if SNAN_BIT_IS_ONE + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); +#else + return ((a & ~0x8000) >= 0x7c80); +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is a signaling +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +int float16_is_signaling_nan(float16 a) +{ +#if SNAN_BIT_IS_ONE + return ((a & ~0x8000) >= 0x7c80); +#else + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); +#endif +} + +/*---------------------------------------------------------------------------- +| Returns a quiet NaN if the half-precision floating point value `a' is a +| signaling NaN; otherwise returns `a'. +*----------------------------------------------------------------------------*/ +float16 float16_maybe_silence_nan(float16 a) +{ + if (float16_is_signaling_nan(a)) { +#if SNAN_BIT_IS_ONE +# if defined(TARGET_MIPS) || defined(TARGET_SH4) + return float16_default_nan; +# else +# error Rules for silencing a signaling NaN are target-specific +# endif +#else + a |= (1 << 9); +#endif + } + return a; +} + +/*---------------------------------------------------------------------------- | The pattern for a default generated single-precision NaN. *----------------------------------------------------------------------------*/ #if defined(TARGET_SPARC) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 17842f4..dc4492a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2713,15 +2713,15 @@ float32 float64_to_float32( float64 a STATUS_PARAM ) | than the desired result exponent whenever `zSig' is a complete, normalized | significand. *----------------------------------------------------------------------------*/ -static bits16 packFloat16(flag zSign, int16 zExp, bits16 zSig) +static float16 packFloat16(flag zSign, int16 zExp, bits16 zSig) { return (((bits32)zSign) << 15) + (((bits32)zExp) << 10) + zSig; } /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ - -float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM ) + +float32 float16_to_float32(float16 a, flag ieee STATUS_PARAM) { flag aSign; int16 aExp; @@ -2753,7 +2753,7 @@ float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM ) return packFloat32( aSign, aExp + 0x70, aSig << 13); } -bits16 float32_to_float16( float32 a, flag ieee STATUS_PARAM) +float16 float32_to_float16(float32 a, flag ieee STATUS_PARAM) { flag aSign; int16 aExp; diff --git a/fpu/softfloat.h b/fpu/softfloat.h index 4a5345c..f773d67 100644 --- a/fpu/softfloat.h +++ b/fpu/softfloat.h @@ -118,6 +118,7 @@ enum { sane ABI should be able to see though these structs. However x86/gcc 3.x seems to struggle a bit, so leave them disabled by default. */ //#define USE_SOFTFLOAT_STRUCT_TYPES +typedef uint16_t float16; #ifdef USE_SOFTFLOAT_STRUCT_TYPES typedef struct { uint32_t v; @@ -253,8 +254,15 @@ float128 int64_to_float128( int64_t STATUS_PARAM ); /*---------------------------------------------------------------------------- | Software half-precision conversion routines. *----------------------------------------------------------------------------*/ -bits16 float32_to_float16( float32, flag STATUS_PARAM ); -float32 float16_to_float32( bits16, flag STATUS_PARAM ); +float16 float32_to_float16( float32, flag STATUS_PARAM ); +float32 float16_to_float32( float16, flag STATUS_PARAM ); + +/*---------------------------------------------------------------------------- +| Software half-precision operations. +*----------------------------------------------------------------------------*/ +int float16_is_quiet_nan( float16 ); +int float16_is_signaling_nan( float16 ); +float16 float16_maybe_silence_nan( float16 ); /*---------------------------------------------------------------------------- | Software IEC/IEEE single-precision conversion routines.