From patchwork Fri Jan 7 22:42:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 77933 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1A32B6F2B for ; Sat, 8 Jan 2011 10:17:33 +1100 (EST) Received: from localhost ([127.0.0.1]:46516 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PbLC6-00066m-B6 for incoming@patchwork.ozlabs.org; Fri, 07 Jan 2011 17:54:02 -0500 Received: from [140.186.70.92] (port=49313 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PbL39-000296-4Y for qemu-devel@nongnu.org; Fri, 07 Jan 2011 17:44:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PbL1o-0003M1-9o for qemu-devel@nongnu.org; Fri, 07 Jan 2011 17:43:25 -0500 Received: from a.mail.sonic.net ([64.142.16.245]:46698) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PbL1o-0003LZ-1D for qemu-devel@nongnu.org; Fri, 07 Jan 2011 17:43:24 -0500 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by a.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p07Mh6VZ001756 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 7 Jan 2011 14:43:06 -0800 Received: from are.twiddle.net (localhost [127.0.0.1]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p07Mh5BJ000941; Fri, 7 Jan 2011 14:43:05 -0800 Received: (from rth@localhost) by are.twiddle.net (8.14.4/8.14.4/Submit) id p07Mh5jv000940; Fri, 7 Jan 2011 14:43:05 -0800 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Jan 2011 14:42:58 -0800 Message-Id: <1294440183-885-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1294440183-885-1-git-send-email-rth@twiddle.net> References: <1294440183-885-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 Cc: Alexander Graf , Aurelien Jarno Subject: [Qemu-devel] [PATCH 2/7] tcg-ppc: Implement deposit operation. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c | 17 ++++++++++++++++- tcg/ppc/tcg-target.h | 1 + 2 files changed, 17 insertions(+), 1 deletions(-) diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 7970268..2947d1b 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -1611,6 +1611,21 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; + case INDEX_op_deposit_i32: + { + unsigned len = args[3] & 31; + unsigned lsb_ofs = (args[3] >> 8) & 31; + unsigned msb_ofs = 31 - lsb_ofs; + + tcg_out32 (s, RLWIMI + | RA(args[0]) + | RS(args[2]) + | SH((32 - msb_ofs - len) & 31) + | MB(msb_ofs) + | ME((msb_ofs + len - 1) & 31)); + } + break; + case INDEX_op_add2_i32: if (args[0] == args[3] || args[0] == args[5]) { tcg_out32 (s, ADDC | TAB (0, args[2], args[4])); @@ -1829,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, { INDEX_op_sar_i32, { "r", "r", "ri" } }, - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, { INDEX_op_rotr_i32, { "r", "r", "ri" } }, + { INDEX_op_deposit_i32, { "r", "0", "r" } }, { INDEX_op_brcond_i32, { "r", "ri" } }, diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index a1f8599..bbf38d5 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -92,6 +92,7 @@ enum { #define TCG_TARGET_HAS_eqv_i32 #define TCG_TARGET_HAS_nand_i32 #define TCG_TARGET_HAS_nor_i32 +#define TCG_TARGET_HAS_deposit_i32 #define TCG_AREG0 TCG_REG_R27