Message ID | 1294342675-20643-3-git-send-email-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
diff --git a/target-arm/helper.c b/target-arm/helper.c index 50c1017..05684a2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2315,7 +2315,7 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val) if (changed & (1 << 25)) set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); - i = vfp_exceptbits_to_host((val >> 8) & 0x1f); + i = vfp_exceptbits_to_host(val); set_float_exception_flags(i, &env->vfp.fp_status); }
When handling a write to the ARM FPSCR, set the softfloat cumulative exception flags from the cumulative flags in the FPSCR, not the exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host will only look at the correct bits anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)