From patchwork Tue Jan 4 15:15:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 77492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 16610B70E7 for ; Wed, 5 Jan 2011 02:17:31 +1100 (EST) Received: from localhost ([127.0.0.1]:59502 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pa8db-0002Bi-K9 for incoming@patchwork.ozlabs.org; Tue, 04 Jan 2011 10:17:27 -0500 Received: from [140.186.70.92] (port=41139 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pa8cJ-00027q-Uf for qemu-devel@nongnu.org; Tue, 04 Jan 2011 10:16:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pa8cI-0004vo-BP for qemu-devel@nongnu.org; Tue, 04 Jan 2011 10:16:07 -0500 Received: from hall.aurel32.net ([88.191.126.93]:37447) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pa8cI-0004uk-6e for qemu-devel@nongnu.org; Tue, 04 Jan 2011 10:16:06 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Pa8cA-0004Nd-0n; Tue, 04 Jan 2011 16:15:58 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.72) (envelope-from ) id 1Pa8c7-0002Fw-W5; Tue, 04 Jan 2011 16:15:56 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 4 Jan 2011 16:15:46 +0100 Message-Id: <1294154150-7528-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1294154150-7528-1-git-send-email-aurelien@aurel32.net> References: <1294154150-7528-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 4/8] softfloat: fix float{32, 64}_maybe_silence_nan() for MIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On targets that define sNaN with the sNaN bit as one, simply clearing this bit may correspond to an infinite value. Convert it to a default NaN if SNAN_BIT_IS_ONE, as it corresponds to the MIPS implementation, the only emulated CPU with SNAN_BIT_IS_ONE. When other CPU of this type are added, this might be updated to include more cases. Signed-off-by: Aurelien Jarno --- fpu/softfloat-specialize.h | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0003cbe..ac26214 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -107,13 +107,17 @@ int float32_is_signaling_nan( float32 a_ ) float32 float32_maybe_silence_nan( float32 a_ ) { if (float32_is_signaling_nan(a_)) { - bits32 a = float32_val(a_); #if SNAN_BIT_IS_ONE - a &= ~(1 << 22); +# if defined(TARGET_MIPS) + return float32_default_nan; +# else +# error Rules for silencing a signaling NaN are target-specific +# endif #else + bits32 a = float32_val(a_); a |= (1 << 22); -#endif return make_float32(a); +#endif } return a_; } @@ -322,13 +326,17 @@ int float64_is_signaling_nan( float64 a_ ) float64 float64_maybe_silence_nan( float64 a_ ) { if (float64_is_signaling_nan(a_)) { - bits64 a = float64_val(a_); #if SNAN_BIT_IS_ONE - a &= ~LIT64( 0x0008000000000000 ); +# if defined(TARGET_MIPS) + return float64_default_nan; +# else +# error Rules for silencing a signaling NaN are target-specific +# endif #else + bits64 a = float64_val(a_); a |= LIT64( 0x0008000000000000 ); -#endif return make_float64(a); +#endif } return a_; }