From patchwork Fri Jul 9 06:38:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 58358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1BB50B7085 for ; Fri, 9 Jul 2010 16:38:04 +1000 (EST) Received: from localhost ([127.0.0.1]:55726 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OX7Dk-0000NS-TG for incoming@patchwork.ozlabs.org; Fri, 09 Jul 2010 02:38:01 -0400 Received: from [140.186.70.92] (port=37447 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OX7CF-0000LC-88 for qemu-devel@nongnu.org; Fri, 09 Jul 2010 02:36:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OX7CD-00047v-CQ for qemu-devel@nongnu.org; Fri, 09 Jul 2010 02:36:26 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:56009) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OX7CD-00047e-7s for qemu-devel@nongnu.org; Fri, 09 Jul 2010 02:36:25 -0400 Received: by pzk10 with SMTP id 10so411050pzk.4 for ; Thu, 08 Jul 2010 23:36:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=dZhue1WUJWVgdbpYA5bcXB6U7z5mG0IJm+Gr4L7AmvA=; b=YFx7PaR0xLJt/Nauh+209yWnYDdenUD/f4dVh4q5zo/zSHBuMK9bT4wvpHztNiiuAd c33KtPW1fgoEkdkoQTzdB7zMCehhLgJjkysGuJQkDw8sGw1iwEcVqmRQYBYbZFHaZymS dzA+r5N+21ME64BWTrCTeb+zIF1BRBT2Idu8s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=PjWhN96EsQ3TDYlQScBOpWpTbG9j31x0f6TyagdrlkT+/rzNm6iTUKL7wz9UfeZrW7 5zmZLwXAqNB/HDLP2ssDPntzsq0xgN0AMpHiRLq1PfMoERg62pAVIsH3zbXNmCSMcPxb D8g3i7FQRbuMZIkdftu9zv4OuJmri7J1UJKiU= Received: by 10.142.193.19 with SMTP id q19mr2211249wff.332.1278657380665; Thu, 08 Jul 2010 23:36:20 -0700 (PDT) Received: from localhost.localdomain (fw-cisco.dcl.info.waseda.ac.jp [133.9.216.204]) by mx.google.com with ESMTPS id r9sm337863rvl.22.2010.07.08.23.36.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 08 Jul 2010 23:36:19 -0700 (PDT) From: Alexandre Courbot To: qemu-devel@nongnu.org Date: Fri, 9 Jul 2010 15:38:35 +0900 Message-Id: <1278657516-26130-2-git-send-email-gnurou@gmail.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1278657516-26130-1-git-send-email-gnurou@gmail.com> References: <1278657516-26130-1-git-send-email-gnurou@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: Alexandre Courbot Subject: [Qemu-devel] [PATCH 1/2] target-sh4: Split the LDST macro into 2 sub-macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The LDST macro is used to generate ldc and stc instructions that work with a specific register. However, the SGR register only supports stc up to SH4A, which supports both stc and ldc. This patch creates two sub-macros named LD and ST that handle generating ldc and stc instructions separately, and redeclares LDST to use these sub-macro. --- target-sh4/translate.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d0d6c00..3abafd0 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1511,7 +1511,7 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free(addr); } return; -#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ +#define LD(reg,ldnum,ldpnum,prechk) \ case ldnum: \ prechk \ tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ @@ -1520,7 +1520,8 @@ static void _decode_opc(DisasContext * ctx) prechk \ tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ - return; \ + return; +#define ST(reg,stnum,stpnum,prechk) \ case stnum: \ prechk \ tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ @@ -1535,6 +1536,9 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free(addr); \ } \ return; +#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ + LD(reg,ldnum,ldpnum,prechk) \ + ST(reg,stnum,stpnum,prechk) LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)