From patchwork Fri Jun 4 19:14:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 54690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AAD2BB7D47 for ; Sat, 5 Jun 2010 05:53:12 +1000 (EST) Received: from localhost ([127.0.0.1]:57825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcwu-0006fB-Qy for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 15:53:01 -0400 Received: from [140.186.70.92] (port=59075 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcO7-0005xl-Mg for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcO6-0002a6-BZ for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:03 -0400 Received: from are.twiddle.net ([75.149.56.221]:54801) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcO4-0002ZY-S8 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:02 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 0903546D; Fri, 4 Jun 2010 12:16:57 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o54JGrlL007284; Fri, 4 Jun 2010 12:16:53 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o54JGoUI007283; Fri, 4 Jun 2010 12:16:50 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 Jun 2010 12:14:32 -0700 Message-Id: <1275678883-7082-25-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 24/35] tcg-s390: Use the XOR IMMEDIATE instructions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 60 +++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 56 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index a17ef91..5446591 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -38,6 +38,7 @@ #define TCG_CT_CONST_ADDI 0x0400 #define TCG_CT_CONST_ANDI 0x1000 #define TCG_CT_CONST_ORI 0x2000 +#define TCG_CT_CONST_XORI 0x4000 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -67,6 +68,8 @@ typedef enum S390Opcode { RIL_NILF = 0xc00b, RIL_OIHF = 0xc00c, RIL_OILF = 0xc00d, + RIL_XIHF = 0xc006, + RIL_XILF = 0xc007, RI_AGHI = 0xa70b, RI_AHI = 0xa70a, @@ -341,6 +344,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) ct->ct &= ~TCG_CT_REG; ct->ct |= TCG_CT_CONST_ORI; break; + case 'X': + ct->ct &= ~TCG_CT_REG; + ct->ct |= TCG_CT_CONST_XORI; + break; default: break; } @@ -437,6 +444,30 @@ static int tcg_match_ori(int ct, tcg_target_long val) return 1; } +/* Immediates to be used with logical XOR. This is almost, but not quite, + only an optimization. XOR with immediate is only supported with the + extended-immediate facility. That said, there are a few patterns for + which it is better to load the value into a register first. */ + +static int tcg_match_xori(int ct, tcg_target_long val) +{ + if ((facilities & FACILITY_EXT_IMM) == 0) { + return 0; + } + + if (ct & TCG_CT_CONST_32) { + /* All 32-bit XORs can be performed with 1 48-bit insn. */ + return 1; + } + + /* Look for negative values. These are best to load with LGHI. */ + if (val < 0 && val == (int32_t)val) { + return 0; + } + + return 1; +} + /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, const TCGArgConstraint *arg_ct) @@ -470,6 +501,8 @@ static int tcg_target_const_match(tcg_target_long val, return tcg_match_andi(ct, val); } else if (ct & TCG_CT_CONST_ORI) { return tcg_match_ori(ct, val); + } else if (ct & TCG_CT_CONST_XORI) { + return tcg_match_xori(ct, val); } return 0; @@ -936,6 +969,17 @@ static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val) } } +static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +{ + /* Perform the xor by parts. */ + if (val & 0xffffffff) { + tcg_out_insn(s, RIL, XILF, dest, val); + } + if (val > 0xffffffff) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + } +} + static void tgen32_cmp(TCGContext *s, TCGCond c, TCGReg r1, TCGReg r2) { if (c > TCG_COND_GT) { @@ -1430,7 +1474,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i32: - tcg_out_insn(s, RR, XR, args[0], args[2]); + if (const_args[2]) { + tgen64_xori(s, args[0], args[2] & 0xffffffff); + } else { + tcg_out_insn(s, RR, XR, args[0], args[2]); + } break; case INDEX_op_and_i64: @@ -1448,7 +1496,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i64: - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + if (const_args[2]) { + tgen64_xori(s, args[0], args[2]); + } else { + tcg_out_insn(s, RRE, XGR, args[0], args[2]); + } break; case INDEX_op_neg_i32: @@ -1710,7 +1762,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_and_i32, { "r", "0", "rWA" } }, { INDEX_op_or_i32, { "r", "0", "rWO" } }, - { INDEX_op_xor_i32, { "r", "0", "r" } }, + { INDEX_op_xor_i32, { "r", "0", "rWX" } }, { INDEX_op_neg_i32, { "r", "r" } }, @@ -1772,7 +1824,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_and_i64, { "r", "0", "rA" } }, { INDEX_op_or_i64, { "r", "0", "rO" } }, - { INDEX_op_xor_i64, { "r", "0", "r" } }, + { INDEX_op_xor_i64, { "r", "0", "rX" } }, { INDEX_op_neg_i64, { "r", "r" } },