From patchwork Fri Jun 4 19:14:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 54686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA29DB7D24 for ; Sat, 5 Jun 2010 05:44:25 +1000 (EST) Received: from localhost ([127.0.0.1]:42491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcng-0002MN-JN for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 15:43:28 -0400 Received: from [140.186.70.92] (port=58905 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcNf-0005bJ-8X for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcNe-0002RY-4S for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:35 -0400 Received: from are.twiddle.net ([75.149.56.221]:54790) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcNc-0002Qv-RI for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:34 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 1381E105F; Fri, 4 Jun 2010 12:16:29 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o54JGPj6007253; Fri, 4 Jun 2010 12:16:25 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o54JGNqa007252; Fri, 4 Jun 2010 12:16:23 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 Jun 2010 12:14:27 -0700 Message-Id: <1275678883-7082-20-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 19/35] tcg-s390: Implement rotates. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ tcg/s390/tcg-target.h | 4 ++-- 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 3a98ca3..f53038b 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -108,6 +108,8 @@ typedef enum S390Opcode { RR_SR = 0x1b, RR_XR = 0x17, + RSY_RLL = 0xeb1d, + RSY_RLLG = 0xeb1c, RSY_SLLG = 0xeb0d, RSY_SRAG = 0xeb0a, RSY_SRLG = 0xeb0c, @@ -1201,6 +1203,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, op = RSY_SRAG; goto do_shift64; + case INDEX_op_rotl_i32: + /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); + } else { + tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); + } + break; + case INDEX_op_rotr_i32: + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLL, args[0], args[1], + TCG_REG_NONE, (32 - args[2]) & 31); + } else { + tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); + tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); + } + break; + + case INDEX_op_rotl_i64: + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], + TCG_REG_NONE, args[2]); + } else { + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); + } + break; + case INDEX_op_rotr_i64: + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], + TCG_REG_NONE, (64 - args[2]) & 63); + } else { + /* We can use the smaller 32-bit negate because only the + low 6 bits are examined for the rotate. */ + tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); + } + break; + case INDEX_op_ext8s_i32: tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); break; @@ -1365,6 +1405,9 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_shr_i32, { "r", "0", "Ri" } }, { INDEX_op_sar_i32, { "r", "0", "Ri" } }, + { INDEX_op_rotl_i32, { "r", "r", "Ri" } }, + { INDEX_op_rotr_i32, { "r", "r", "Ri" } }, + { INDEX_op_ext8s_i32, { "r", "r" } }, { INDEX_op_ext8u_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, @@ -1423,6 +1466,9 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_shr_i64, { "r", "r", "Ri" } }, { INDEX_op_sar_i64, { "r", "r", "Ri" } }, + { INDEX_op_rotl_i64, { "r", "r", "Ri" } }, + { INDEX_op_rotr_i64, { "r", "r", "Ri" } }, + { INDEX_op_ext8s_i64, { "r", "r" } }, { INDEX_op_ext8u_i64, { "r", "r" } }, { INDEX_op_ext16s_i64, { "r", "r" } }, diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index dcb9bc3..9135c7a 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -49,7 +49,7 @@ typedef enum TCGReg { /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 -// #define TCG_TARGET_HAS_rot_i32 +#define TCG_TARGET_HAS_rot_i32 #define TCG_TARGET_HAS_ext8s_i32 #define TCG_TARGET_HAS_ext16s_i32 #define TCG_TARGET_HAS_ext8u_i32 @@ -65,7 +65,7 @@ typedef enum TCGReg { // #define TCG_TARGET_HAS_nor_i32 #define TCG_TARGET_HAS_div2_i64 -// #define TCG_TARGET_HAS_rot_i64 +#define TCG_TARGET_HAS_rot_i64 #define TCG_TARGET_HAS_ext8s_i64 #define TCG_TARGET_HAS_ext16s_i64 #define TCG_TARGET_HAS_ext32s_i64