From patchwork Thu May 27 20:46:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 50B72B7D1B for ; Fri, 28 May 2010 08:38:01 +1000 (EST) Received: from localhost ([127.0.0.1]:45801 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHli9-0007QW-TO for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 18:37:58 -0400 Received: from [140.186.70.92] (port=56375 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjzg-0002Oc-RE for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjzd-0005TQ-Nz for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:56 -0400 Received: from are.twiddle.net ([75.149.56.221]:51267) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjzd-0005TD-Bd for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:53 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id D1C7B576; Thu, 27 May 2010 13:47:52 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlqSb031044; Thu, 27 May 2010 13:47:52 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlp0k031041; Thu, 27 May 2010 13:47:51 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:31 -0700 Message-Id: <1274993204-30766-50-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 49/62] tcg-s390: Conditionalize LOAD IMMEDIATE instructions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The LOAD IMMEDIATE and (some of) the LOAD LOGICAL IMMEDIATE instructions are in the extended-immediate facility. Begin making that facility optional by using these only if present. Thankfully, the LOAD ADDRESS RELATIVE and the LOAD LOGICAL IMMEDIATE insns with 16-bit constants are always available. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 79 ++++++++++++++++++++++++++++++++++++------------ 1 files changed, 59 insertions(+), 20 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index b66778a..491de07 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -491,7 +491,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, sval = (int32_t)sval; } - /* First, try all 32-bit insns that can load it in one go. */ + /* Try all 32-bit insns that can load it in one go. */ if (sval >= -0x8000 && sval < 0x8000) { tcg_out_insn(s, RI, LGHI, ret, sval); return; @@ -505,22 +505,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } - /* Second, try all 48-bit insns that can load it in one go. */ - if (sval == (int32_t)sval) { - tcg_out_insn(s, RIL, LGFI, ret, sval); - return; - } - if (uval <= 0xffffffff) { - tcg_out_insn(s, RIL, LLILF, ret, uval); - return; - } - if ((uval & 0xffffffff) == 0) { - tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); - return; + /* Try all 48-bit insns that can load it in one go. */ + if (facilities & FACILITY_EXT_IMM) { + if (sval == (int32_t)sval) { + tcg_out_insn(s, RIL, LGFI, ret, sval); + return; + } + if (uval <= 0xffffffff) { + tcg_out_insn(s, RIL, LLILF, ret, uval); + return; + } + if ((uval & 0xffffffff) == 0) { + tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); + return; + } } - /* If we get here, both the high and low parts have non-zero bits. */ - /* Try for PC-relative address load. */ if ((sval & 1) == 0) { intptr_t off = (sval - (intptr_t)s->code_ptr) >> 1; @@ -530,17 +530,56 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } + /* If extended immediates are not present, then we may have to issue + several instructions to load the low 32 bits. */ + if (!(facilities & FACILITY_EXT_IMM)) { + /* A 32-bit unsigned value can be loaded in 2 insns. And given + that the lli_insns loop above did not succeed, we know that + both insns are required. */ + if (uval <= 0xffffffff) { + tcg_out_insn(s, RI, LLILL, ret, uval); + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } + + /* If all high bits are set, the value can be loaded in 2 or 3 insns. + We first want to make sure that all the high bits get set. With + luck the low 16-bits can be considered negative to perform that for + free, otherwise we load an explicit -1. */ + if (sval >> 32 == -1) { + if (uval & 0x8000) { + tcg_out_insn(s, RI, LGHI, ret, uval); + } else { + tcg_out_insn(s, RI, LGHI, ret, -1); + tcg_out_insn(s, RI, IILL, ret, uval); + } + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } + } + + /* If we get here, both the high and low parts have non-zero bits. */ + /* Recurse to load the lower 32-bits. */ tcg_out_movi(s, TCG_TYPE_I32, ret, sval); /* Insert data into the high 32-bits. */ uval >>= 32; - if (uval < 0x10000) { - tcg_out_insn(s, RI, IIHL, ret, uval); - } else if ((uval & 0xffff) == 0) { - tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + if (facilities & FACILITY_EXT_IMM) { + if (uval < 0x10000) { + tcg_out_insn(s, RI, IIHL, ret, uval); + } else if ((uval & 0xffff) == 0) { + tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + } else { + tcg_out_insn(s, RIL, IIHF, ret, uval); + } } else { - tcg_out_insn(s, RIL, IIHF, ret, uval); + if (uval & 0xffff) { + tcg_out_insn(s, RI, IIHL, ret, uval); + } + if (uval & 0xffff0000) { + tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + } } }