From patchwork Thu May 27 20:46:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 915A7B7D1D for ; Fri, 28 May 2010 07:52:17 +1000 (EST) Received: from localhost ([127.0.0.1]:44176 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHkzF-0004Xg-2Z for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:51:33 -0400 Received: from [140.186.70.92] (port=56183 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjzM-0002Br-MV for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjzL-0005Oo-ET for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:36 -0400 Received: from are.twiddle.net ([75.149.56.221]:51237) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjzL-0005Oi-4X for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:35 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 8853D576; Thu, 27 May 2010 13:47:34 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlXbA030977; Thu, 27 May 2010 13:47:33 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlXIu030976; Thu, 27 May 2010 13:47:33 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:17 -0700 Message-Id: <1274993204-30766-36-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 35/62] tcg-s390: Implement immediate XORs. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 45 +++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 41 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 1bc9b4c..ec8c84d 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -57,6 +57,8 @@ typedef enum S390Opcode { RIL_NILF = 0xc00b, RIL_OIHF = 0xc00c, RIL_OILF = 0xc00d, + RIL_XIHF = 0xc006, + RIL_XILF = 0xc007, RI_AGHI = 0xa70b, RI_AHI = 0xa70a, @@ -719,6 +721,33 @@ static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val) tgen64_ori(s, dest, val & 0xffffffff00000000ull); } +static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +{ + tcg_target_long sval = val; + + /* Zero-th, look for no-op. */ + if (val == 0) { + return; + } + + /* First, look for 64-bit values for which it is better to load the + value first and perform the xor via registers. This is true for + any 32-bit negative value, where the high 32-bits get flipped too. */ + if (sval < 0 && sval == (int32_t)sval) { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R13, sval); + tcg_out_insn(s, RRE, XGR, dest, TCG_REG_R13); + return; + } + + /* Second, perform the xor by parts. */ + if (val & 0xffffffff) { + tcg_out_insn(s, RIL, XILF, dest, val); + } + if (val > 0xffffffff) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + } +} + static void tgen32_cmp(TCGContext *s, TCGCond c, TCGReg r1, TCGReg r2) { if (c > TCG_COND_GT) { @@ -1202,7 +1231,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i32: - tcg_out_insn(s, RR, XR, args[0], args[2]); + if (const_args[2]) { + tgen64_xori(s, args[0], args[2] & 0xffffffff); + } else { + tcg_out_insn(s, RR, XR, args[0], args[2]); + } break; case INDEX_op_and_i64: @@ -1220,7 +1253,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i64: - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + if (const_args[2]) { + tgen64_xori(s, args[0], args[2]); + } else { + tcg_out_insn(s, RRE, XGR, args[0], args[2]); + } break; case INDEX_op_neg_i32: @@ -1490,7 +1527,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_and_i32, { "r", "0", "ri" } }, { INDEX_op_or_i32, { "r", "0", "ri" } }, - { INDEX_op_xor_i32, { "r", "0", "r" } }, + { INDEX_op_xor_i32, { "r", "0", "ri" } }, { INDEX_op_neg_i32, { "r", "r" } }, { INDEX_op_shl_i32, { "r", "0", "Ri" } }, @@ -1551,7 +1588,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_and_i64, { "r", "0", "ri" } }, { INDEX_op_or_i64, { "r", "0", "ri" } }, - { INDEX_op_xor_i64, { "r", "0", "r" } }, + { INDEX_op_xor_i64, { "r", "0", "ri" } }, { INDEX_op_neg_i64, { "r", "r" } }, { INDEX_op_shl_i64, { "r", "r", "Ri" } },