From patchwork Thu May 27 20:46:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0F8DBB7D27 for ; Fri, 28 May 2010 07:22:13 +1000 (EST) Received: from localhost ([127.0.0.1]:56871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHkWn-0000CH-HW for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:22:09 -0400 Received: from [140.186.70.92] (port=55881 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjz0-0001x0-3W for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjyy-0005Hg-Ml for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:13 -0400 Received: from are.twiddle.net ([75.149.56.221]:51197) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjyy-0005Hc-Bd for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:12 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id C682947E; Thu, 27 May 2010 13:47:11 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlB95030909; Thu, 27 May 2010 13:47:11 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlAef030908; Thu, 27 May 2010 13:47:10 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:00 -0700 Message-Id: <1274993204-30766-19-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 18/62] tcg-s390: Use matching constraints. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Simplify the generation within tcg_out_op by forcing arg1 == arg0 for the two-operand instructions. In addition, fix the use of the 64-bit shift insns in implementing the 32-bit shifts. This would yield incorrect results for the right shifts. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 181 +++++++++++-------------------------------------- 1 files changed, 39 insertions(+), 142 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 0deb332..c45d8b5 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -683,7 +683,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { TCGLabel* l; - S390Opcode op, op2; + S390Opcode op; switch (opc) { case INDEX_op_exit_tb: @@ -842,111 +842,43 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_add_i32: if (const_args[2]) { - if (args[0] == args[1]) { - tcg_out_insn(s, RI, AHI, args[1], args[2]); - } else { - tcg_out_insn(s, RR, LR, args[0], args[1]); - tcg_out_insn(s, RI, AHI, args[0], args[2]); - } - } else if (args[0] == args[1]) { - tcg_out_insn(s, RR, AR, args[1], args[2]); - } else if (args[0] == args[2]) { - tcg_out_insn(s, RR, AR, args[0], args[1]); + tcg_out_insn(s, RI, AHI, args[0], args[2]); } else { - tcg_out_insn(s, RR, LR, args[0], args[1]); tcg_out_insn(s, RR, AR, args[0], args[2]); } break; - case INDEX_op_sub_i32: - if (args[0] == args[1]) { - /* sr %ra0/1, %ra2 */ - tcg_out_insn(s, RR, SR, args[1], args[2]); - } else if (args[0] == args[2]) { - /* lr %r13, %raa0/2 */ - tcg_out_insn(s, RR, LR, TCG_REG_R13, args[2]); - /* lr %ra0/2, %ra1 */ - tcg_out_insn(s, RR, LR, args[0], args[1]); - /* sr %ra0/2, %r13 */ - tcg_out_insn(s, RR, SR, args[0], TCG_REG_R13); - } else { - /* lr %ra0, %ra1 */ - tcg_out_insn(s, RR, LR, args[0], args[1]); - /* sr %ra0, %ra2 */ - tcg_out_insn(s, RR, SR, args[0], args[2]); - } + case INDEX_op_add_i64: + tcg_out_insn(s, RRE, AGR, args[0], args[2]); break; - case INDEX_op_sub_i64: - if (args[0] == args[1]) { - /* sgr %ra0/1, %ra2 */ - tcg_out_insn(s, RRE, SGR, args[1], args[2]); - } else if (args[0] == args[2]) { - tcg_out_mov(s, TCG_REG_R13, args[2]); - tcg_out_mov(s, args[0], args[1]); - /* sgr %ra0/2, %r13 */ - tcg_out_insn(s, RRE, SGR, args[0], TCG_REG_R13); - } else { - tcg_out_mov(s, args[0], args[1]); - /* sgr %ra0, %ra2 */ - tcg_out_insn(s, RRE, SGR, args[0], args[2]); - } + case INDEX_op_sub_i32: + tcg_out_insn(s, RR, SR, args[0], args[2]); break; - case INDEX_op_add_i64: - if (args[0] == args[1]) { - tcg_out_insn(s, RRE, AGR, args[1], args[2]); - } else if (args[0] == args[2]) { - tcg_out_insn(s, RRE, AGR, args[0], args[1]); - } else { - tcg_out_mov(s, args[0], args[1]); - tcg_out_insn(s, RRE, AGR, args[0], args[2]); - } + case INDEX_op_sub_i64: + tcg_out_insn(s, RRE, SGR, args[0], args[2]); break; case INDEX_op_and_i32: - op = RR_NR; - do_logic_i32: - if (args[0] == args[1]) { - /* xr %ra0/1, %ra2 */ - tcg_out_insn_RR(s, op, args[1], args[2]); - } else if (args[0] == args[2]) { - /* xr %ra0/2, %ra1 */ - tcg_out_insn_RR(s, op, args[0], args[1]); - } else { - /* lr %ra0, %ra1 */ - tcg_out_insn(s, RR, LR, args[0], args[1]); - /* xr %ra0, %ra2 */ - tcg_out_insn_RR(s, op, args[0], args[2]); - } + tcg_out_insn(s, RR, NR, args[0], args[2]); break; - case INDEX_op_or_i32: - op = RR_OR; - goto do_logic_i32; + tcg_out_insn(s, RR, OR, args[0], args[2]); + break; case INDEX_op_xor_i32: - op = RR_XR; - goto do_logic_i32; + tcg_out_insn(s, RR, XR, args[0], args[2]); + break; case INDEX_op_and_i64: - op = RRE_NGR; - do_logic_i64: - if (args[0] == args[1]) { - tcg_out_insn_RRE(s, op, args[0], args[2]); - } else if (args[0] == args[2]) { - tcg_out_insn_RRE(s, op, args[0], args[1]); - } else { - tcg_out_mov(s, args[0], args[1]); - tcg_out_insn_RRE(s, op, args[0], args[2]); - } + tcg_out_insn(s, RRE, NGR, args[0], args[2]); break; - case INDEX_op_or_i64: - op = RRE_OGR; - goto do_logic_i64; + tcg_out_insn(s, RRE, OGR, args[0], args[2]); + break; case INDEX_op_xor_i64: - op = RRE_XGR; - goto do_logic_i64; + tcg_out_insn(s, RRE, XGR, args[0], args[2]); + break; case INDEX_op_neg_i32: /* FIXME: optimize args[0] != args[1] case */ @@ -954,7 +886,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); tcg_out_insn(s, RR, SR, args[0], 13); break; - case INDEX_op_neg_i64: /* FIXME: optimize args[0] != args[1] case */ tcg_out_mov(s, TCG_REG_R13, args[1]); @@ -963,28 +894,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mul_i32: - if (args[0] == args[1]) - /* msr %ra0/1, %ra2 */ - tcg_out_insn(s, RRE, MSR, args[0], args[2]); - else if (args[0] == args[2]) - /* msr %ra0/2, %ra1 */ - tcg_out_insn(s, RRE, MSR, args[0], args[1]); - else { - tcg_out_insn(s, RR, LR, args[0], args[1]); - /* msr %ra0, %ra2 */ - tcg_out_insn(s, RRE, MSR, args[0], args[2]); - } + tcg_out_insn(s, RRE, MSR, args[0], args[2]); break; - case INDEX_op_mul_i64: - if (args[0] == args[1]) { - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); - } else if (args[0] == args[2]) { - tcg_out_insn(s, RRE, MSGR, args[0], args[1]); - } else { - /* XXX */ - tcg_abort(); - } + tcg_out_insn(s, RRE, MSGR, args[0], args[2]); break; case INDEX_op_divu_i32: @@ -1001,32 +914,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i32: op = RS_SLL; - op2 = RSY_SLLG; do_shift32: if (const_args[2]) { - if (args[0] == args[1]) { - tcg_out_sh32(s, op, args[0], SH32_REG_NONE, args[2]); - } else { - tcg_out_insn(s, RR, LR, args[0], args[1]); - tcg_out_sh32(s, op, args[0], SH32_REG_NONE, args[2]); - } + tcg_out_sh32(s, op, args[0], SH32_REG_NONE, args[2]); } else { - if (args[0] == args[1]) { - tcg_out_sh32(s, op, args[0], args[2], 0); - } else { - tcg_out_sh64(s, op2, args[0], args[1], args[2], 0); - } + tcg_out_sh32(s, op, args[0], args[2], 0); } break; - case INDEX_op_shr_i32: op = RS_SRL; - op2 = RSY_SRLG; goto do_shift32; - case INDEX_op_sar_i32: op = RS_SRA; - op2 = RSY_SRAG; goto do_shift32; case INDEX_op_shl_i64: @@ -1038,11 +937,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_sh64(s, op, args[0], args[1], args[2], 0); } break; - case INDEX_op_shr_i64: op = RSY_SRLG; goto do_shift64; - case INDEX_op_sar_i64: op = RSY_SRAG; goto do_shift64; @@ -1146,7 +1043,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } - static const TCGTargetOpDef s390_op_defs[] = { +static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_exit_tb, { } }, { INDEX_op_goto_tb, { } }, { INDEX_op_call, { "ri" } }, @@ -1165,23 +1062,23 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, { INDEX_op_st16_i32, { "r", "r" } }, { INDEX_op_st_i32, { "r", "r" } }, - { INDEX_op_add_i32, { "r", "r", "rI" } }, - { INDEX_op_sub_i32, { "r", "r", "r" } }, - { INDEX_op_mul_i32, { "r", "r", "r" } }, + { INDEX_op_add_i32, { "r", "0", "rI" } }, + { INDEX_op_sub_i32, { "r", "0", "r" } }, + { INDEX_op_mul_i32, { "r", "0", "r" } }, { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, { INDEX_op_rem_i32, { "r", "r", "r" } }, { INDEX_op_remu_i32, { "r", "r", "r" } }, - { INDEX_op_and_i32, { "r", "r", "r" } }, - { INDEX_op_or_i32, { "r", "r", "r" } }, - { INDEX_op_xor_i32, { "r", "r", "r" } }, + { INDEX_op_and_i32, { "r", "0", "r" } }, + { INDEX_op_or_i32, { "r", "0", "r" } }, + { INDEX_op_xor_i32, { "r", "0", "r" } }, { INDEX_op_neg_i32, { "r", "r" } }, - { INDEX_op_shl_i32, { "r", "r", "Ri" } }, - { INDEX_op_shr_i32, { "r", "r", "Ri" } }, - { INDEX_op_sar_i32, { "r", "r", "Ri" } }, + { INDEX_op_shl_i32, { "r", "0", "Ri" } }, + { INDEX_op_shr_i32, { "r", "0", "Ri" } }, + { INDEX_op_sar_i32, { "r", "0", "Ri" } }, { INDEX_op_brcond_i32, { "r", "r" } }, @@ -1216,13 +1113,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, { INDEX_op_qemu_ld64, { "L", "L" } }, { INDEX_op_qemu_st64, { "L", "L" } }, - { INDEX_op_add_i64, { "r", "r", "r" } }, - { INDEX_op_mul_i64, { "r", "r", "r" } }, - { INDEX_op_sub_i64, { "r", "r", "r" } }, + { INDEX_op_add_i64, { "r", "0", "r" } }, + { INDEX_op_sub_i64, { "r", "0", "r" } }, + { INDEX_op_mul_i64, { "r", "0", "r" } }, - { INDEX_op_and_i64, { "r", "r", "r" } }, - { INDEX_op_or_i64, { "r", "r", "r" } }, - { INDEX_op_xor_i64, { "r", "r", "r" } }, + { INDEX_op_and_i64, { "r", "0", "r" } }, + { INDEX_op_or_i64, { "r", "0", "r" } }, + { INDEX_op_xor_i64, { "r", "0", "r" } }, { INDEX_op_neg_i64, { "r", "r" } }, { INDEX_op_shl_i64, { "r", "r", "Ri" } }, @@ -1233,7 +1130,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, #endif { -1 }, - }; +}; void tcg_target_init(TCGContext *s) {