From patchwork Thu May 27 20:45:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53818 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) by ozlabs.org (Postfix) with ESMTP id 266DFB7D1B for ; Fri, 28 May 2010 07:37:50 +1000 (EST) Received: from localhost ([127.0.0.1]:54131 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHkgm-0005RH-Pl for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:32:29 -0400 Received: from [140.186.70.92] (port=55877 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjyz-0001wv-Ui for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjyu-0005Ge-Qf for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:13 -0400 Received: from are.twiddle.net ([75.149.56.221]:51189) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjyu-0005GR-5Q for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:08 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 9D933576; Thu, 27 May 2010 13:47:07 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKl7d1030897; Thu, 27 May 2010 13:47:07 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKl6QU030896; Thu, 27 May 2010 13:47:06 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:45:57 -0700 Message-Id: <1274993204-30766-16-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 15/62] tcg-s390: Update disassembler from binutils head. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- s390-dis.c | 818 +++++++++++++++++++++++++++++++++++++++++++++++++----------- 1 files changed, 669 insertions(+), 149 deletions(-) diff --git a/s390-dis.c b/s390-dis.c index 86dd84f..1284f20 100644 --- a/s390-dis.c +++ b/s390-dis.c @@ -1,34 +1,39 @@ +/* opcodes/s390-dis.c revision 1.18 */ /* s390-dis.c -- Disassemble S390 instructions - Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. + Copyright 2000, 2001, 2002, 2003, 2005, 2007, 2008 + Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - This file is part of GDB, GAS and the GNU binutils. + This file is part of the GNU opcodes library. - This program is free software; you can redistribute it and/or modify + This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + the Free Software Foundation; either version 3, or (at your option) + any later version. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, see . */ + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ -#include +#include "qemu-common.h" #include "dis-asm.h" +/* include/opcode/s390.h revision 1.10 */ /* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001, 2003 Free Software Foundation, Inc. + Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of BFD, the Binary File Descriptor library. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or + the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, @@ -37,7 +42,9 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, see . */ + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ #ifndef S390_H #define S390_H @@ -57,7 +64,8 @@ enum s390_opcode_cpu_val S390_OPCODE_Z900, S390_OPCODE_Z990, S390_OPCODE_Z9_109, - S390_OPCODE_Z9_EC + S390_OPCODE_Z9_EC, + S390_OPCODE_Z10 }; /* The opcode table is an array of struct s390_opcode. */ @@ -95,12 +103,13 @@ struct s390_opcode /* The table itself is sorted by major opcode number, and is otherwise in the order in which the disassembler should consider instructions. */ -extern const struct s390_opcode s390_opcodes[]; -extern const int s390_num_opcodes; +/* QEMU: Mark these static. */ +static const struct s390_opcode s390_opcodes[]; +static const int s390_num_opcodes; /* A opcode format table for the .insn pseudo mnemonic. */ -extern const struct s390_opcode s390_opformats[]; -extern const int s390_num_opformats; +static const struct s390_opcode s390_opformats[]; +static const int s390_num_opformats; /* Values defined for the flags field of a struct powerpc_opcode. */ @@ -164,12 +173,13 @@ extern const struct s390_operand s390_operands[]; the instruction may be optional. */ #define S390_OPERAND_OPTIONAL 0x400 - #endif /* S390_H */ - +#endif /* S390_H */ static int init_flag = 0; static int opc_index[256]; -static int current_arch_mask = 0; + +/* QEMU: Just set mask to include all architectures. */ +static int current_arch_mask = -1; /* Set up index table for first opcode byte. */ @@ -178,6 +188,9 @@ init_disasm (struct disassemble_info *info) { const struct s390_opcode *opcode; const struct s390_opcode *opcode_end; +#ifdef QEMU_DISABLE + const char *p; +#endif memset (opc_index, 0, sizeof (opc_index)); opcode_end = s390_opcodes + s390_num_opcodes; @@ -188,21 +201,44 @@ init_disasm (struct disassemble_info *info) (opcode[1].opcode[0] == opcode->opcode[0])) opcode++; } -// switch (info->mach) -// { -// case bfd_mach_s390_31: - current_arch_mask = 1 << S390_OPCODE_ESA; -// break; -// case bfd_mach_s390_64: -// current_arch_mask = 1 << S390_OPCODE_ZARCH; -// break; -// default: -// abort (); -// } + +#ifdef QEMU_DISABLE + for (p = info->disassembler_options; p != NULL; ) + { + if (CONST_STRNEQ (p, "esa")) + current_arch_mask = 1 << S390_OPCODE_ESA; + else if (CONST_STRNEQ (p, "zarch")) + current_arch_mask = 1 << S390_OPCODE_ZARCH; + else + fprintf (stderr, "Unknown S/390 disassembler option: %s\n", p); + + p = strchr (p, ','); + if (p != NULL) + p++; + } + + if (!current_arch_mask) + switch (info->mach) + { + case bfd_mach_s390_31: + current_arch_mask = 1 << S390_OPCODE_ESA; + break; + case bfd_mach_s390_64: + current_arch_mask = 1 << S390_OPCODE_ZARCH; + break; + default: + abort (); + } +#endif /* QEMU_DISABLE */ + init_flag = 1; } /* Extracts an operand value from an instruction. */ +/* We do not perform the shift operation for larl-type address + operands here since that would lead to an overflow of the 32 bit + integer value. Instead the shift operation is done when printing + the operand in print_insn_s390. */ static inline unsigned int s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) @@ -233,10 +269,6 @@ s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) && (val & (1U << (operand->bits - 1)))) val |= (-1U << (operand->bits - 1)) << 1; - /* Double value if the operand is pc relative. */ - if (operand->flags & S390_OPERAND_PCREL) - val <<= 1; - /* Length x in an instructions has real length x + 1. */ if (operand->flags & S390_OPERAND_LENGTH) val++; @@ -318,8 +350,6 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) separator = 0; for (opindex = opcode->operands; *opindex != 0; opindex++) { - unsigned int value; - operand = s390_operands + *opindex; value = s390_extract_operand (buffer, operand); @@ -344,7 +374,8 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) else if (operand->flags & S390_OPERAND_CR) (*info->fprintf_func) (info->stream, "%%c%i", value); else if (operand->flags & S390_OPERAND_PCREL) - (*info->print_address_func) (memaddr + (int) value, info); + (*info->print_address_func) (memaddr + (int)value + (int)value, + info); else if (operand->flags & S390_OPERAND_SIGNED) (*info->fprintf_func) (info->stream, "%i", (int) value); else @@ -392,26 +423,48 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) return 1; } } + +#ifdef QEMU_DISABLE +void +print_s390_disassembler_options (FILE *stream) +{ + fprintf (stream, _("\n\ +The following S/390 specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _(" esa Disassemble in ESA architecture mode\n")); + fprintf (stream, _(" zarch Disassemble in z/Architecture mode\n")); +} +#endif + +/* include opcodes/s390-opc.c revision 1.24 */ /* s390-opc.c -- S390 opcode list - Copyright 2000, 2001, 2003 Free Software Foundation, Inc. + Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009 + Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - This file is part of GDB, GAS, and the GNU binutils. + This file is part of the GNU opcodes library. - This program is free software; you can redistribute it and/or modify + This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + the Free Software Foundation; either version 3, or (at your option) + any later version. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, see . */ + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ +#ifdef QEMU_DISABLE #include +#include "ansidecl.h" +#include "opcode/s390.h" +#endif /* This file holds the S390 opcode table. The opcode table includes almost all of the extended instruction mnemonics. This @@ -432,100 +485,143 @@ const struct s390_operand s390_operands[] = #define UNUSED 0 { 0, 0, 0 }, /* Indicates the end of the operand list */ +/* General purpose register operands. */ + #define R_8 1 /* GPR starting at position 8 */ { 4, 8, S390_OPERAND_GPR }, #define R_12 2 /* GPR starting at position 12 */ { 4, 12, S390_OPERAND_GPR }, -#define R_16 3 /* GPR starting at position 16 */ +#define RO_12 3 /* optional GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR|S390_OPERAND_OPTIONAL }, +#define R_16 4 /* GPR starting at position 16 */ { 4, 16, S390_OPERAND_GPR }, -#define R_20 4 /* GPR starting at position 20 */ +#define R_20 5 /* GPR starting at position 20 */ { 4, 20, S390_OPERAND_GPR }, -#define R_24 5 /* GPR starting at position 24 */ +#define R_24 6 /* GPR starting at position 24 */ { 4, 24, S390_OPERAND_GPR }, -#define R_28 6 /* GPR starting at position 28 */ +#define R_28 7 /* GPR starting at position 28 */ { 4, 28, S390_OPERAND_GPR }, -#define R_32 7 /* GPR starting at position 32 */ +#define RO_28 8 /* optional GPR starting at position 28 */ + { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, +#define R_32 9 /* GPR starting at position 32 */ { 4, 32, S390_OPERAND_GPR }, -#define F_8 8 /* FPR starting at position 8 */ +/* Floating point register operands. */ + +#define F_8 10 /* FPR starting at position 8 */ { 4, 8, S390_OPERAND_FPR }, -#define F_12 9 /* FPR starting at position 12 */ +#define F_12 11 /* FPR starting at position 12 */ { 4, 12, S390_OPERAND_FPR }, -#define F_16 10 /* FPR starting at position 16 */ +#define F_16 12 /* FPR starting at position 16 */ { 4, 16, S390_OPERAND_FPR }, -#define F_20 11 /* FPR starting at position 16 */ +#define F_20 13 /* FPR starting at position 16 */ { 4, 16, S390_OPERAND_FPR }, -#define F_24 12 /* FPR starting at position 24 */ +#define F_24 14 /* FPR starting at position 24 */ { 4, 24, S390_OPERAND_FPR }, -#define F_28 13 /* FPR starting at position 28 */ +#define F_28 15 /* FPR starting at position 28 */ { 4, 28, S390_OPERAND_FPR }, -#define F_32 14 /* FPR starting at position 32 */ +#define F_32 16 /* FPR starting at position 32 */ { 4, 32, S390_OPERAND_FPR }, -#define A_8 15 /* Access reg. starting at position 8 */ +/* Access register operands. */ + +#define A_8 17 /* Access reg. starting at position 8 */ { 4, 8, S390_OPERAND_AR }, -#define A_12 16 /* Access reg. starting at position 12 */ +#define A_12 18 /* Access reg. starting at position 12 */ { 4, 12, S390_OPERAND_AR }, -#define A_24 17 /* Access reg. starting at position 24 */ +#define A_24 19 /* Access reg. starting at position 24 */ { 4, 24, S390_OPERAND_AR }, -#define A_28 18 /* Access reg. starting at position 28 */ +#define A_28 20 /* Access reg. starting at position 28 */ { 4, 28, S390_OPERAND_AR }, -#define C_8 19 /* Control reg. starting at position 8 */ +/* Control register operands. */ + +#define C_8 21 /* Control reg. starting at position 8 */ { 4, 8, S390_OPERAND_CR }, -#define C_12 20 /* Control reg. starting at position 12 */ +#define C_12 22 /* Control reg. starting at position 12 */ { 4, 12, S390_OPERAND_CR }, -#define B_16 21 /* Base register starting at position 16 */ +/* Base register operands. */ + +#define B_16 23 /* Base register starting at position 16 */ { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, -#define B_32 22 /* Base register starting at position 32 */ +#define B_32 24 /* Base register starting at position 32 */ { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, -#define X_12 23 /* Index register starting at position 12 */ +#define X_12 25 /* Index register starting at position 12 */ { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, -#define D_20 24 /* Displacement starting at position 20 */ +/* Address displacement operands. */ + +#define D_20 26 /* Displacement starting at position 20 */ { 12, 20, S390_OPERAND_DISP }, -#define D_36 25 /* Displacement starting at position 36 */ +#define DO_20 27 /* optional Displ. starting at position 20 */ + { 12, 20, S390_OPERAND_DISP|S390_OPERAND_OPTIONAL }, +#define D_36 28 /* Displacement starting at position 36 */ { 12, 36, S390_OPERAND_DISP }, -#define D20_20 26 /* 20 bit displacement starting at 20 */ +#define D20_20 29 /* 20 bit displacement starting at 20 */ { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, -#define L4_8 27 /* 4 bit length starting at position 8 */ +/* Length operands. */ + +#define L4_8 30 /* 4 bit length starting at position 8 */ { 4, 8, S390_OPERAND_LENGTH }, -#define L4_12 28 /* 4 bit length starting at position 12 */ +#define L4_12 31 /* 4 bit length starting at position 12 */ { 4, 12, S390_OPERAND_LENGTH }, -#define L8_8 29 /* 8 bit length starting at position 8 */ +#define L8_8 32 /* 8 bit length starting at position 8 */ { 8, 8, S390_OPERAND_LENGTH }, -#define U4_8 30 /* 4 bit unsigned value starting at 8 */ +/* Signed immediate operands. */ + +#define I8_8 33 /* 8 bit signed value starting at 8 */ + { 8, 8, S390_OPERAND_SIGNED }, +#define I8_32 34 /* 8 bit signed value starting at 32 */ + { 8, 32, S390_OPERAND_SIGNED }, +#define I16_16 35 /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +#define I16_32 36 /* 16 bit signed value starting at 32 */ + { 16, 32, S390_OPERAND_SIGNED }, +#define I32_16 37 /* 32 bit signed value starting at 16 */ + { 32, 16, S390_OPERAND_SIGNED }, + +/* Unsigned immediate operands. */ + +#define U4_8 38 /* 4 bit unsigned value starting at 8 */ { 4, 8, 0 }, -#define U4_12 31 /* 4 bit unsigned value starting at 12 */ +#define U4_12 39 /* 4 bit unsigned value starting at 12 */ { 4, 12, 0 }, -#define U4_16 32 /* 4 bit unsigned value starting at 16 */ +#define U4_16 40 /* 4 bit unsigned value starting at 16 */ { 4, 16, 0 }, -#define U4_20 33 /* 4 bit unsigned value starting at 20 */ +#define U4_20 41 /* 4 bit unsigned value starting at 20 */ { 4, 20, 0 }, -#define U8_8 34 /* 8 bit unsigned value starting at 8 */ +#define U4_32 42 /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, +#define U8_8 43 /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 35 /* 8 bit unsigned value starting at 16 */ +#define U8_16 44 /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define I16_16 36 /* 16 bit signed value starting at 16 */ - { 16, 16, S390_OPERAND_SIGNED }, -#define U16_16 37 /* 16 bit unsigned value starting at 16 */ +#define U8_24 45 /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +#define U8_32 46 /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +#define U16_16 47 /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define J16_16 38 /* PC relative jump offset at 16 */ +#define U16_32 48 /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +#define U32_16 49 /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + +/* PC-relative address operands. */ + +#define J16_16 50 /* PC relative jump offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J32_16 39 /* PC relative long offset at 16 */ +#define J32_16 51 /* PC relative long offset at 16 */ { 32, 16, S390_OPERAND_PCREL }, -#define I32_16 40 /* 32 bit signed value starting at 16 */ - { 32, 16, S390_OPERAND_SIGNED }, -#define U32_16 41 /* 32 bit unsigned value starting at 16 */ - { 32, 16, 0 }, -#define M_16 42 /* 4 bit optional mask starting at 16 */ + +/* Conditional mask operands. */ + +#define M_16 52 /* 4 bit optional mask starting at 16 */ { 4, 16, S390_OPERAND_OPTIONAL }, -#define RO_28 43 /* optional GPR starting at position 28 */ - { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) } }; @@ -563,7 +659,7 @@ const struct s390_operand s390_operands[] = quite close. For example the instruction "mvo" is defined in the PoP as follows: - + MVO D1(L1,B1),D2(L2,B2) [SS] -------------------------------------- @@ -575,6 +671,17 @@ const struct s390_operand s390_operands[] = #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ +#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ +#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ +#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ +#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ +#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ +#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ +#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ +#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ +#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ +#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ @@ -585,6 +692,10 @@ const struct s390_operand s390_operands[] = #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ +#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ +#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ +#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ @@ -604,24 +715,29 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ -#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ +#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ -#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ +#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ +#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ +#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +#define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ +#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ +#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ -#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ +#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ @@ -638,12 +754,17 @@ const struct s390_operand s390_operands[] = #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ +#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +#define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ +#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ +#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ +#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ @@ -652,12 +773,23 @@ const struct s390_operand s390_operands[] = #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ -#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } @@ -668,6 +800,10 @@ const struct s390_operand s390_operands[] = #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } @@ -690,15 +826,20 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } -#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } @@ -719,12 +860,17 @@ const struct s390_operand s390_operands[] = #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -733,22 +879,26 @@ const struct s390_operand s390_operands[] = #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } + /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ -const struct s390_opcode s390_opformats[] = +/* QEMU: Mark these static. */ +static const struct s390_opcode s390_opformats[] = { { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, @@ -760,14 +910,16 @@ const struct s390_opcode s390_opformats[] = { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, }; -const int s390_num_opformats = +static const int s390_num_opformats = sizeof (s390_opformats) / sizeof (s390_opformats[0]); +/* include "s390-opc.tab", generated from opcodes/s390-opc.txt revision 1.28 */ /* The opcode table. This file was generated by s390-mkopc. The format of the opcode table is: @@ -783,7 +935,8 @@ const int s390_num_opformats = The disassembler reads the table in order and prints the first instruction which matches. */ -const struct s390_opcode s390_opcodes[] = +/* QEMU: Mark these static. */ +static const struct s390_opcode s390_opcodes[] = { { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, @@ -801,12 +954,12 @@ const struct s390_opcode s390_opcodes[] = { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, - { "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, - { "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, - { "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, - { "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, - { "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, - { "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, + { "tdgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, + { "tdcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, + { "tdgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, + { "tdcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, + { "tdget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, + { "tdcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, { "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, { "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, @@ -820,6 +973,7 @@ const struct s390_opcode s390_opcodes[] = { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, + { "sqd", OP48(0xed0000000035LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, @@ -852,6 +1006,270 @@ const struct s390_opcode s390_opcodes[] = { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, + { "clibnh", OP48(0xec0c000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clible", OP48(0xec0c000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cibnh", OP48(0xec0c000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cible", OP48(0xec0c000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clgibnh", OP48(0xec0c000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clgible", OP48(0xec0c000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cgibnh", OP48(0xec0c000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cgible", OP48(0xec0c000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clijnh", OP48(0xec0c0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clijle", OP48(0xec0c0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cijnh", OP48(0xec0c0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cijle", OP48(0xec0c0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clgijnh", OP48(0xec0c0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clgijle", OP48(0xec0c0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cgijnh", OP48(0xec0c0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cgijle", OP48(0xec0c0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clibnl", OP48(0xec0a000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clibhe", OP48(0xec0a000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cibnl", OP48(0xec0a000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cibhe", OP48(0xec0a000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clgibnl", OP48(0xec0a000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clgibhe", OP48(0xec0a000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cgibnl", OP48(0xec0a000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cgibhe", OP48(0xec0a000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clijnl", OP48(0xec0a0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clijhe", OP48(0xec0a0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cijnl", OP48(0xec0a0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cijhe", OP48(0xec0a0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clgijnl", OP48(0xec0a0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clgijhe", OP48(0xec0a0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cgijnl", OP48(0xec0a0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cgijhe", OP48(0xec0a0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clibe", OP48(0xec08000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clibnlh", OP48(0xec08000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cibe", OP48(0xec08000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cibnlh", OP48(0xec08000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clgibe", OP48(0xec08000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clgibnlh", OP48(0xec08000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cgibe", OP48(0xec08000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cgibnlh", OP48(0xec08000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clije", OP48(0xec080000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clijnlh", OP48(0xec080000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cije", OP48(0xec080000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cijnlh", OP48(0xec080000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clgije", OP48(0xec080000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clgijnlh", OP48(0xec080000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cgije", OP48(0xec080000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cgijnlh", OP48(0xec080000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clibne", OP48(0xec06000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cliblh", OP48(0xec06000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cibne", OP48(0xec06000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "ciblh", OP48(0xec06000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clgibne", OP48(0xec06000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clgiblh", OP48(0xec06000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cgibne", OP48(0xec06000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cgiblh", OP48(0xec06000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clijne", OP48(0xec060000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clijlh", OP48(0xec060000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cijne", OP48(0xec060000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cijlh", OP48(0xec060000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clgijne", OP48(0xec060000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clgijlh", OP48(0xec060000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cgijne", OP48(0xec060000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cgijlh", OP48(0xec060000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clibl", OP48(0xec04000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clibnhe", OP48(0xec04000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cibl", OP48(0xec04000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cibnhe", OP48(0xec04000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clgibl", OP48(0xec04000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clgibnhe", OP48(0xec04000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cgibl", OP48(0xec04000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cgibnhe", OP48(0xec04000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clijl", OP48(0xec040000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clijnhe", OP48(0xec040000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cijl", OP48(0xec040000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cijnhe", OP48(0xec040000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clgijl", OP48(0xec040000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clgijnhe", OP48(0xec040000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cgijl", OP48(0xec040000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cgijnhe", OP48(0xec040000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clibh", OP48(0xec02000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clibnle", OP48(0xec02000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cibh", OP48(0xec02000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cibnle", OP48(0xec02000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clgibh", OP48(0xec02000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "clgibnle", OP48(0xec02000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6}, + { "cgibh", OP48(0xec02000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "cgibnle", OP48(0xec02000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6}, + { "clijh", OP48(0xec020000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clijnle", OP48(0xec020000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cijh", OP48(0xec020000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cijnle", OP48(0xec020000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clgijh", OP48(0xec020000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "clgijnle", OP48(0xec020000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6}, + { "cgijh", OP48(0xec020000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "cgijnle", OP48(0xec020000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6}, + { "clrbnh", OP48(0xec000000c0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrble", OP48(0xec000000c0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbnh", OP48(0xec000000c0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crble", OP48(0xec000000c0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbnh", OP48(0xec000000c0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrble", OP48(0xec000000c0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbnh", OP48(0xec000000c0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrble", OP48(0xec000000c0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrjnh", OP48(0xec000000c077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clrjle", OP48(0xec000000c077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjnh", OP48(0xec000000c076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjle", OP48(0xec000000c076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clfitnh", OP48(0xec000000c073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clfitle", OP48(0xec000000c073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "citnh", OP48(0xec000000c072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "citle", OP48(0xec000000c072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgitnh", OP48(0xec000000c071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clgitle", OP48(0xec000000c071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cgitnh", OP48(0xec000000c070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cgitle", OP48(0xec000000c070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgrjnh", OP48(0xec000000c065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clgrjle", OP48(0xec000000c065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "cgrjnh", OP48(0xec000000c064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "cgrjle", OP48(0xec000000c064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "clrbnl", OP48(0xec000000a0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrbhe", OP48(0xec000000a0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbnl", OP48(0xec000000a0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbhe", OP48(0xec000000a0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbnl", OP48(0xec000000a0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbhe", OP48(0xec000000a0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbnl", OP48(0xec000000a0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbhe", OP48(0xec000000a0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrjnl", OP48(0xec000000a077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clrjhe", OP48(0xec000000a077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjnl", OP48(0xec000000a076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjhe", OP48(0xec000000a076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clfitnl", OP48(0xec000000a073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clfithe", OP48(0xec000000a073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "citnl", OP48(0xec000000a072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cithe", OP48(0xec000000a072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgitnl", OP48(0xec000000a071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clgithe", OP48(0xec000000a071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cgitnl", OP48(0xec000000a070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cgithe", OP48(0xec000000a070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgrjnl", OP48(0xec000000a065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clgrjhe", OP48(0xec000000a065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "cgrjnl", OP48(0xec000000a064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "cgrjhe", OP48(0xec000000a064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "clrbe", OP48(0xec00000080f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrbnlh", OP48(0xec00000080f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbe", OP48(0xec00000080f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbnlh", OP48(0xec00000080f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbe", OP48(0xec00000080e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbnlh", OP48(0xec00000080e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbe", OP48(0xec00000080e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbnlh", OP48(0xec00000080e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrje", OP48(0xec0000008077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clrjnlh", OP48(0xec0000008077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crje", OP48(0xec0000008076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjnlh", OP48(0xec0000008076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clfite", OP48(0xec0000008073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clfitnlh", OP48(0xec0000008073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cite", OP48(0xec0000008072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "citnlh", OP48(0xec0000008072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgite", OP48(0xec0000008071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clgitnlh", OP48(0xec0000008071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cgite", OP48(0xec0000008070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cgitnlh", OP48(0xec0000008070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgrje", OP48(0xec0000008065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clgrjnlh", OP48(0xec0000008065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "cgrje", OP48(0xec0000008064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "cgrjnlh", OP48(0xec0000008064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "clrbne", OP48(0xec00000060f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrblh", OP48(0xec00000060f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbne", OP48(0xec00000060f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crblh", OP48(0xec00000060f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbne", OP48(0xec00000060e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrblh", OP48(0xec00000060e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbne", OP48(0xec00000060e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrblh", OP48(0xec00000060e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrjne", OP48(0xec0000006077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clrjlh", OP48(0xec0000006077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjne", OP48(0xec0000006076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjlh", OP48(0xec0000006076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clfitne", OP48(0xec0000006073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clfitlh", OP48(0xec0000006073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "citne", OP48(0xec0000006072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "citlh", OP48(0xec0000006072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgitne", OP48(0xec0000006071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clgitlh", OP48(0xec0000006071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cgitne", OP48(0xec0000006070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cgitlh", OP48(0xec0000006070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgrjne", OP48(0xec0000006065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clgrjlh", OP48(0xec0000006065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "cgrjne", OP48(0xec0000006064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "cgrjlh", OP48(0xec0000006064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "clrbl", OP48(0xec00000040f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrbnhe", OP48(0xec00000040f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbl", OP48(0xec00000040f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbnhe", OP48(0xec00000040f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbl", OP48(0xec00000040e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbnhe", OP48(0xec00000040e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbl", OP48(0xec00000040e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbnhe", OP48(0xec00000040e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrjl", OP48(0xec0000004077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clrjnhe", OP48(0xec0000004077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjl", OP48(0xec0000004076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjnhe", OP48(0xec0000004076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clfitl", OP48(0xec0000004073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clfitnhe", OP48(0xec0000004073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "citl", OP48(0xec0000004072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "citnhe", OP48(0xec0000004072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgitl", OP48(0xec0000004071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clgitnhe", OP48(0xec0000004071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cgitl", OP48(0xec0000004070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cgitnhe", OP48(0xec0000004070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgrjl", OP48(0xec0000004065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clgrjnhe", OP48(0xec0000004065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "cgrjl", OP48(0xec0000004064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "cgrjnhe", OP48(0xec0000004064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "clrbh", OP48(0xec00000020f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrbnle", OP48(0xec00000020f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbh", OP48(0xec00000020f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "crbnle", OP48(0xec00000020f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbh", OP48(0xec00000020e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clgrbnle", OP48(0xec00000020e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbh", OP48(0xec00000020e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "cgrbnle", OP48(0xec00000020e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6}, + { "clrjh", OP48(0xec0000002077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clrjnle", OP48(0xec0000002077LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjh", OP48(0xec0000002076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "crjnle", OP48(0xec0000002076LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clfith", OP48(0xec0000002073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clfitnle", OP48(0xec0000002073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cith", OP48(0xec0000002072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "citnle", OP48(0xec0000002072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgith", OP48(0xec0000002071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "clgitnle", OP48(0xec0000002071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6}, + { "cgith", OP48(0xec0000002070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "cgitnle", OP48(0xec0000002070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6}, + { "clgrjh", OP48(0xec0000002065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "clgrjnle", OP48(0xec0000002065LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 6}, + { "cgrjh", OP48(0xec0000002064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "cgrjnle", OP48(0xec0000002064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6}, + { "clib", OP48(0xec00000000ffLL), MASK_RIS_RURDU, INSTR_RIS_RURDU, 2, 6}, + { "cib", OP48(0xec00000000feLL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 2, 6}, + { "clgib", OP48(0xec00000000fdLL), MASK_RIS_RURDU, INSTR_RIS_RURDU, 2, 6}, + { "cgib", OP48(0xec00000000fcLL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 2, 6}, + { "clrb", OP48(0xec00000000f7LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6}, + { "crb", OP48(0xec00000000f6LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6}, + { "clgrb", OP48(0xec00000000e5LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6}, + { "cgrb", OP48(0xec00000000e4LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6}, + { "clij", OP48(0xec000000007fLL), MASK_RIE_RUPU, INSTR_RIE_RUPU, 2, 6}, + { "cij", OP48(0xec000000007eLL), MASK_RIE_RUPI, INSTR_RIE_RUPI, 2, 6}, + { "clgij", OP48(0xec000000007dLL), MASK_RIE_RUPU, INSTR_RIE_RUPU, 2, 6}, + { "cgij", OP48(0xec000000007cLL), MASK_RIE_RUPI, INSTR_RIE_RUPI, 2, 6}, + { "clrj", OP48(0xec0000000077LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6}, + { "crj", OP48(0xec0000000076LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6}, + { "clfit", OP48(0xec0000000073LL), MASK_RIE_R0UU, INSTR_RIE_R0UU, 2, 6}, + { "cit", OP48(0xec0000000072LL), MASK_RIE_R0IU, INSTR_RIE_R0IU, 2, 6}, + { "clgit", OP48(0xec0000000071LL), MASK_RIE_R0UU, INSTR_RIE_R0UU, 2, 6}, + { "cgit", OP48(0xec0000000070LL), MASK_RIE_R0IU, INSTR_RIE_R0IU, 2, 6}, + { "clgrj", OP48(0xec0000000065LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6}, + { "cgrj", OP48(0xec0000000064LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6}, + { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6}, + { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6}, + { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6}, + { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6}, { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2}, { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2}, { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0}, @@ -861,18 +1279,23 @@ const struct s390_opcode s390_opcodes[] = { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, - { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, + { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3}, { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3}, { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0}, { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, + { "algsi", OP48(0xeb000000007eLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6}, + { "agsi", OP48(0xeb000000007aLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6}, + { "alsi", OP48(0xeb000000006eLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6}, + { "asi", OP48(0xeb000000006aLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6}, { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, + { "ecag", OP48(0xeb000000004cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 6}, { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, @@ -916,6 +1339,15 @@ const struct s390_opcode s390_opcodes[] = { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0}, { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, + { "clfhsi", OP16(0xe55dLL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6}, + { "chsi", OP16(0xe55cLL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6}, + { "clghsi", OP16(0xe559LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6}, + { "cghsi", OP16(0xe558LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6}, + { "clhhsi", OP16(0xe555LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6}, + { "chhsi", OP16(0xe554LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6}, + { "mvhi", OP16(0xe54cLL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6}, + { "mvghi", OP16(0xe548LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6}, + { "mvhhi", OP16(0xe544LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6}, { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, @@ -953,18 +1385,21 @@ const struct s390_opcode s390_opcodes[] = { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, + { "mhy", OP48(0xe3000000007cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6}, { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, + { "laey", OP48(0xe30000000075LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6}, { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, + { "mfy", OP48(0xe3000000005cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6}, { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, @@ -981,6 +1416,9 @@ const struct s390_opcode s390_opcodes[] = { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, + { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 2, 6}, + { "cgh", OP48(0xe30000000034LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6}, + { "ltgf", OP48(0xe30000000032LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6}, { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, @@ -1063,6 +1501,29 @@ const struct s390_opcode s390_opcodes[] = { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5}, { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5}, { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4}, + { "clrl", OP16(0xc60fLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "clgfrl", OP16(0xc60eLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "crl", OP16(0xc60dLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "cgfrl", OP16(0xc60cLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "clgrl", OP16(0xc60aLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "cgrl", OP16(0xc608LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "clhrl", OP16(0xc607LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "clghrl", OP16(0xc606LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "chrl", OP16(0xc605LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "cghrl", OP16(0xc604LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "pfdrl", OP16(0xc602LL), MASK_RIL_UP, INSTR_RIL_UP, 2, 6}, + { "exrl", OP16(0xc600LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "strl", OP16(0xc40fLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "llgfrl", OP16(0xc40eLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "lrl", OP16(0xc40dLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "lgfrl", OP16(0xc40cLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "stgrl", OP16(0xc40bLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "lgrl", OP16(0xc408LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "sthrl", OP16(0xc407LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "llghrl", OP16(0xc406LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "lhrl", OP16(0xc405LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "lghrl", OP16(0xc404LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, + { "llhrl", OP16(0xc402LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6}, { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, @@ -1073,6 +1534,8 @@ const struct s390_opcode s390_opcodes[] = { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, + { "msfi", OP16(0xc201LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 6}, + { "msgfi", OP16(0xc200LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 6}, { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, @@ -1113,11 +1576,15 @@ const struct s390_opcode s390_opcodes[] = { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, { "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, - { "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, - { "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, + { "trte", OP16(0xb9bfLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 6}, + { "trtre", OP16(0xb9bdLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 6}, + { "cu42", OP16(0xb9b3LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, + { "cu41", OP16(0xb9b2LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, { "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, { "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, + { "pfmf", OP16(0xb9afLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6}, { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4}, + { "ptf", OP16(0xb9a2LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 6}, { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2}, { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, @@ -1146,6 +1613,58 @@ const struct s390_opcode s390_opcodes[] = { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, + { "clrtnh", OP48(0xb973c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtle", OP48(0xb973c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtnl", OP48(0xb973a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrthe", OP48(0xb973a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrte", OP48(0xb97380000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtnlh", OP48(0xb97380000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtne", OP48(0xb97360000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtlh", OP48(0xb97360000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtl", OP48(0xb97340000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtnhe", OP48(0xb97340000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrth", OP48(0xb97320000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrtnle", OP48(0xb97320000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clrt", OP16(0xb973LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6}, + { "crtnh", OP48(0xb972c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtle", OP48(0xb972c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtnl", OP48(0xb972a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crthe", OP48(0xb972a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crte", OP48(0xb97280000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtnlh", OP48(0xb97280000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtne", OP48(0xb97260000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtlh", OP48(0xb97260000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtl", OP48(0xb97240000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtnhe", OP48(0xb97240000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crth", OP48(0xb97220000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crtnle", OP48(0xb97220000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "crt", OP16(0xb972LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6}, + { "clgrtnh", OP48(0xb961c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtle", OP48(0xb961c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtnl", OP48(0xb961a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrthe", OP48(0xb961a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrte", OP48(0xb96180000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtnlh", OP48(0xb96180000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtne", OP48(0xb96160000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtlh", OP48(0xb96160000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtl", OP48(0xb96140000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtnhe", OP48(0xb96140000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrth", OP48(0xb96120000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrtnle", OP48(0xb96120000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "clgrt", OP16(0xb961LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6}, + { "cgrtnh", OP48(0xb960c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtle", OP48(0xb960c0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtnl", OP48(0xb960a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrthe", OP48(0xb960a0000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrte", OP48(0xb96080000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtnlh", OP48(0xb96080000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtne", OP48(0xb96060000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtlh", OP48(0xb96060000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtl", OP48(0xb96040000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtnhe", OP48(0xb96040000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrth", OP48(0xb96020000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrtnle", OP48(0xb96020000000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6}, + { "cgrt", OP16(0xb960LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6}, { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, @@ -1191,16 +1710,16 @@ const struct s390_opcode s390_opcodes[] = { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0}, { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0}, - { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, + { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFRU, INSTR_RRF_FFRU, 2, 5}, { "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5}, - { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, + { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 2, 5}, { "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, { "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, - { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, + { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFRU, INSTR_RRF_FFRU, 2, 5}, { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5}, - { "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, + { "qadtr", OP16(0xb3f5LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 2, 5}, { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, @@ -1239,52 +1758,52 @@ const struct s390_opcode s390_opcodes[] = { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, - { "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, - { "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, - { "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, + { "cxgr", OP16(0xb3c6LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2}, + { "cdgr", OP16(0xb3c5LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2}, + { "cegr", OP16(0xb3c4LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2}, { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, - { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, - { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, - { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, - { "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, - { "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, - { "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, + { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 2}, + { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 2}, + { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 2}, + { "cxfr", OP16(0xb3b6LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0}, + { "cdfr", OP16(0xb3b5LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0}, + { "cefr", OP16(0xb3b4LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0}, { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, - { "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, - { "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, - { "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, + { "cxgbr", OP16(0xb3a6LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2}, + { "cdgbr", OP16(0xb3a5LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2}, + { "cegbr", OP16(0xb3a4LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2}, { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, - { "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, - { "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, - { "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, + { "cxfbr", OP16(0xb396LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0}, + { "cdfbr", OP16(0xb395LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0}, + { "cefbr", OP16(0xb394LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0}, { "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0}, { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5}, { "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0}, - { "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, - { "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, - { "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, - { "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, - { "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, + { "fidr", OP16(0xb37fLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, + { "fier", OP16(0xb377LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, + { "lzxr", OP16(0xb376LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, + { "lzdr", OP16(0xb375LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, + { "lzer", OP16(0xb374LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5}, { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, { "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, - { "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, + { "fixr", OP16(0xb367LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, - { "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, + { "lxr", OP16(0xb365LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0}, - { "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, - { "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, + { "thdr", OP16(0xb359LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, + { "thder", OP16(0xb358LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0}, { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, @@ -1374,7 +1893,6 @@ const struct s390_opcode s390_opcodes[] = { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0}, { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0}, { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, - { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, @@ -1394,8 +1912,8 @@ const struct s390_opcode s390_opcodes[] = { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0}, { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, - { "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, - { "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, + { "sqer", OP16(0xb245LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, + { "sqdr", OP16(0xb244LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0}, @@ -1413,7 +1931,7 @@ const struct s390_opcode s390_opcodes[] = { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0}, { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, - { "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, + { "dxr", OP16(0xb22dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, { "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0}, { "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, @@ -1445,6 +1963,7 @@ const struct s390_opcode s390_opcodes[] = { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0}, { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0}, { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, + { "mc", OP16(0xaf00LL), MASK_SI_URD, INSTR_SI_URD, 2, 6}, { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, @@ -1598,7 +2117,7 @@ const struct s390_opcode s390_opcodes[] = { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0}, - { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, + { "nop", OP16(0x4700LL), MASK_RX_0RRD_OPT, INSTR_RX_0RRD_OPT, 3, 0}, { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, @@ -1685,7 +2204,7 @@ const struct s390_opcode s390_opcodes[] = { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0}, - { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, + { "nopr", OP16(0x0700LL), MASK_RR_0R_OPT, INSTR_RR_0R_OPT, 3, 0}, { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0}, @@ -1696,9 +2215,10 @@ const struct s390_opcode s390_opcodes[] = { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2}, { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5}, { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0}, + { "ptff", OP16(0x0104LL), MASK_E, INSTR_E, 2, 4}, { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0}, { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0} }; -const int s390_num_opcodes = +static const int s390_num_opcodes = sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);