@@ -338,7 +338,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
/* mem_data */
sysbus_mmio_map(s, 3, mem_base);
d = FROM_SYSBUS(APBState, s);
- d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
+ d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci.0",
pci_apb_set_irq, pci_pbm_map_irq, d,
0, 32);
pci_bus_set_mem_base(d->host_state.bus, mem_base);
@@ -88,7 +88,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
qdev_init_nofail(dev);
s = sysbus_from_qdev(dev);
d = FROM_SYSBUS(GrackleState, s);
- d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
+ d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci.0",
pci_grackle_set_irq,
pci_grackle_map_irq,
pic, 0, 4);
@@ -1113,7 +1113,7 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
s = qemu_mallocz(sizeof(GT64120State));
s->pci = qemu_mallocz(sizeof(GT64120PCIState));
- s->pci->bus = pci_register_bus(NULL, "pci",
+ s->pci->bus = pci_register_bus(NULL, "pci.0",
pci_gt64120_set_irq, pci_gt64120_map_irq,
pic, 144, 4);
s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
@@ -357,7 +357,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
controller = qemu_mallocz(sizeof(PPC4xxPCIState));
- controller->pci_state.bus = pci_register_bus(NULL, "pci",
+ controller->pci_state.bus = pci_register_bus(NULL, "pci.0",
ppc4xx_pci_set_irq,
ppc4xx_pci_map_irq,
pci_irqs, 0, 4);
@@ -276,7 +276,7 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
controller = qemu_mallocz(sizeof(PPCE500PCIState));
- controller->pci_state.bus = pci_register_bus(NULL, "pci",
+ controller->pci_state.bus = pci_register_bus(NULL, "pci.0",
mpc85xx_pci_set_irq,
mpc85xx_pci_map_irq,
pci_irqs, 0x88, 4);
@@ -117,7 +117,7 @@ PCIBus *pci_prep_init(qemu_irq *pic)
int PPC_io_memory;
s = qemu_mallocz(sizeof(PREPPCIState));
- s->bus = pci_register_bus(NULL, "pci",
+ s->bus = pci_register_bus(NULL, "pci.0",
prep_set_irq, prep_map_irq, pic, 0, 4);
pci_host_conf_register_ioport(0xcf8, s);
@@ -98,7 +98,7 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
int reg;
p = qemu_mallocz(sizeof(SHPCIC));
- p->bus = pci_register_bus(NULL, "pci",
+ p->bus = pci_register_bus(NULL, "pci.0",
set_irq, map_irq, opaque, devfn_min, nirq);
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
@@ -226,7 +226,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
qdev_init_nofail(dev);
s = sysbus_from_qdev(dev);
d = FROM_SYSBUS(UNINState, s);
- d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
+ d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci.0",
pci_unin_set_irq, pci_unin_map_irq,
pic, 11 << 3, 4);
@@ -278,7 +278,7 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic)
s = sysbus_from_qdev(dev);
d = FROM_SYSBUS(UNINState, s);
- d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
+ d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci.0",
pci_unin_set_irq, pci_unin_map_irq,
pic, 11 << 3, 4);
@@ -125,7 +125,7 @@ static int pci_vpb_init(SysBusDevice *dev)
for (i = 0; i < 4; i++) {
sysbus_init_irq(dev, &s->irq[i]);
}
- bus = pci_register_bus(&dev->qdev, "pci",
+ bus = pci_register_bus(&dev->qdev, "pci.0",
pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
11 << 3, 4);
The system emulators for each arch are using inconsistent naming for the default PCI bus "pci" vs "pci.0". Since it is conceivable we'll have multiple PCI buses in the future standardize on "pci.0" for all architectures. This ensures mgmt apps can rely on a name when assigning PCI devices an address on the bus using eg '-device e1000,bus=pci.0,addr=3' Signed-off-by: Daniel P. Berrange <berrange@redhat.com> --- hw/apb_pci.c | 2 +- hw/grackle_pci.c | 2 +- hw/gt64xxx.c | 2 +- hw/ppc4xx_pci.c | 2 +- hw/ppce500_pci.c | 2 +- hw/prep_pci.c | 2 +- hw/sh_pci.c | 2 +- hw/unin_pci.c | 4 ++-- hw/versatile_pci.c | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-)