From patchwork Sat Apr 10 01:33:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 49895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 511D2B7CF8 for ; Sat, 10 Apr 2010 12:12:49 +1000 (EST) Received: from localhost ([127.0.0.1]:48764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0QBa-0006rN-43 for incoming@patchwork.ozlabs.org; Fri, 09 Apr 2010 22:12:38 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O0Pa3-0004tm-90 for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:51 -0400 Received: from [140.186.70.92] (port=49647 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0Pa0-0004qI-0I for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O0PZp-0007LC-CK for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:47 -0400 Received: from hall.aurel32.net ([88.191.82.174]:35066) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O0PZo-0007Kr-Sl for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:37 -0400 Received: from [10.243.122.2] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O0PZk-0005Mt-Gk; Sat, 10 Apr 2010 03:33:36 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1O0PZV-0004kl-02; Sat, 10 Apr 2010 03:33:17 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 10 Apr 2010 03:33:03 +0200 Message-Id: <1270863186-10180-16-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1270863186-10180-1-git-send-email-aurelien@aurel32.net> References: <1270863186-10180-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Andrzej Zaborowski , Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 15/18] tcg/arm: remove useless register tests in qemu_ld/st X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the constraints. Don't check if they equals these registers. Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 30 ++++++++++-------------------- 1 files changed, 10 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index bb5422d..0627eca 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1048,10 +1048,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) # if TARGET_LONG_BITS == 32 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index); # else - if (addr_reg2 != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index); # endif tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] - @@ -1257,10 +1255,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_out_b(s, COND_EQ, 8); /* TODO: move this code to where the constants pool will be */ - if (addr_reg != TCG_REG_R0) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0)); # if TARGET_LONG_BITS == 32 switch (opc) { case 0: @@ -1272,17 +1268,13 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index); break; case 2: - if (data_reg != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index); break; case 3: - if (data_reg != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); if (data_reg2 != TCG_REG_R2) { tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, data_reg2, SHIFT_IMM_LSL(0)); @@ -1291,10 +1283,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) break; } # else - if (addr_reg2 != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); switch (opc) { case 0: tcg_out_ext8u(s, COND_AL, TCG_REG_R2, data_reg);