From patchwork Fri Apr 9 15:28:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Weil X-Patchwork-Id: 49849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id ED6A2B7CF6 for ; Sat, 10 Apr 2010 01:29:49 +1000 (EST) Received: from localhost ([127.0.0.1]:53474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0G9R-0006vd-Od for incoming@patchwork.ozlabs.org; Fri, 09 Apr 2010 11:29:45 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O0G8o-0006vY-7Y for qemu-devel@nongnu.org; Fri, 09 Apr 2010 11:29:06 -0400 Received: from [140.186.70.92] (port=34621 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0G8m-0006vQ-W3 for qemu-devel@nongnu.org; Fri, 09 Apr 2010 11:29:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O0G8k-0000MX-TC for qemu-devel@nongnu.org; Fri, 09 Apr 2010 11:29:04 -0400 Received: from moutng.kundenserver.de ([212.227.17.8]:51476) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O0G8k-0000Lo-HX for qemu-devel@nongnu.org; Fri, 09 Apr 2010 11:29:02 -0400 Received: from flocke.weilnetz.de (p54ADF948.dip.t-dialin.net [84.173.249.72]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0LqYDd-1NMXX10q37-00eQjP; Fri, 09 Apr 2010 17:28:50 +0200 Received: from stefan by flocke.weilnetz.de with local (Exim 4.71) (envelope-from ) id 1O0G8X-0000A3-6l; Fri, 09 Apr 2010 17:28:49 +0200 From: Stefan Weil To: QEMU Developers Date: Fri, 9 Apr 2010 17:28:40 +0200 Message-Id: <1270826920-590-1-git-send-email-weil@mail.berlios.de> X-Mailer: git-send-email 1.7.0 In-Reply-To: <4BBF3D8D.8040300@twiddle.net> References: <4BBF3D8D.8040300@twiddle.net> X-Provags-ID: V01U2FsdGVkX18AWnENfAgzAx+1v+OHgnWPTSxDvVvrhzLp2cI Kx0+3JK5n/YJGqP3h2phK0cME2MI6J04z5PGOBHeCId/ei5MmQ COBhWz8qrDwk7xlLMOg2gjQjKD/Yo7QGRMUmo9gBEDkt7md7qx InA== X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH] tcp/mips: Change TCG_AREG0 (fp -> s0) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Register fp (frame pointer) is a bad choice for compilations without optimisation, because the compiler makes heavy use of this register (so the resulting code crashes). Register s0 had been used for TCG_AREG1 in earlier releases, but was no longer used and is now free for TCG_AREG0. The resulting code works for compilations without optimisation (tested with qemu mips in qemu mips on x86 host). v2: * Remove s0 from tcg_target_callee_save_regs and add fp there. Hint from Aurelien Jarno, thanks. * Add fp to list of reserved registers. v3: * Don't add fp to list of reserved registers Thanks to Richard Henderson. * Remove s0 from tcg_target_reg_alloc_order. Cc: Aurelien Jarno Cc: Richard Henderson Signed-off-by: Stefan Weil --- dyngen-exec.h | 2 +- tcg/mips/tcg-target.c | 7 +++++-- tcg/mips/tcg-target.h | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/dyngen-exec.h b/dyngen-exec.h index d04eda8..0700a2d 100644 --- a/dyngen-exec.h +++ b/dyngen-exec.h @@ -59,7 +59,7 @@ extern int printf(const char *, ...); #elif defined(__hppa__) #define AREG0 "r17" #elif defined(__mips__) -#define AREG0 "fp" +#define AREG0 "s0" #elif defined(__sparc__) #ifdef CONFIG_SOLARIS #define AREG0 "g2" diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index f4fb615..31296fc 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -69,7 +69,9 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { /* check if we really need so many registers :P */ static const int tcg_target_reg_alloc_order[] = { +#if 0 /* used for the global env (TCG_AREG0), so don't use it here */ TCG_REG_S0, +#endif TCG_REG_S1, TCG_REG_S2, TCG_REG_S3, @@ -1450,7 +1452,9 @@ static const TCGTargetOpDef mips_op_defs[] = { }; static int tcg_target_callee_save_regs[] = { +#if 0 /* used for the global env (TCG_AREG0), so no need to save */ TCG_REG_S0, +#endif TCG_REG_S1, TCG_REG_S2, TCG_REG_S3, @@ -1459,8 +1463,7 @@ static int tcg_target_callee_save_regs[] = { TCG_REG_S6, TCG_REG_S7, TCG_REG_GP, - /* TCG_REG_FP, */ /* currently used for the global env, so np - need to save */ + TCG_REG_FP, TCG_REG_RA, /* should be last for ABI compliance */ }; diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 0292d33..0028bfa 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -97,7 +97,7 @@ enum { #undef TCG_TARGET_HAS_ext16u_i32 /* andi rt, rs, 0xffff */ /* Note: must be synced with dyngen-exec.h */ -#define TCG_AREG0 TCG_REG_FP +#define TCG_AREG0 TCG_REG_S0 /* guest base is supported */ #define TCG_TARGET_HAS_GUEST_BASE