From patchwork Tue Apr 6 00:51:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshiaki Tamura X-Patchwork-Id: 49475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 40364B7D15 for ; Tue, 6 Apr 2010 11:04:59 +1000 (EST) Received: from localhost ([127.0.0.1]:53957 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NyxDs-0004Aa-8e for incoming@patchwork.ozlabs.org; Mon, 05 Apr 2010 21:04:56 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nyx6L-0001uJ-IX for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:57:09 -0400 Received: from [140.186.70.92] (port=43955 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nyx6J-0001tS-1m for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:57:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nyx6C-0001g2-Ov for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:57:06 -0400 Received: from sh.osrg.net ([192.16.179.4]:60021) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nyx6B-0001er-E7 for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:56:59 -0400 Received: from fs.osrg.net (postfix@fs.osrg.net [10.0.0.12]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o360uoSI018684; Tue, 6 Apr 2010 09:56:50 +0900 Received: from localhost (hype-wd0.osrg.net [10.72.1.16]) by fs.osrg.net (Postfix) with ESMTP id 39E3F3E02ED; Tue, 6 Apr 2010 09:56:50 +0900 (JST) From: Yoshiaki Tamura To: kvm@vger.kernel.org, qemu-devel@nongnu.org Date: Tue, 6 Apr 2010 09:51:22 +0900 Message-Id: <1270515084-24120-5-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Mailer: git-send-email 1.7.0.31.g1df487 In-Reply-To: <1270515084-24120-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> References: <1270515084-24120-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Dispatcher: imput version 20070423(IM149) Lines: 107 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Tue, 06 Apr 2010 09:56:52 +0900 (JST) X-Virus-Scanned: clamav-milter 0.95.3 at sh X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aliguori@us.ibm.com, ohmura.kei@lab.ntt.co.jp, mtosatti@redhat.com, Yoshiaki Tamura , avi@redhat.com Subject: [Qemu-devel] [PATCH v2 4/6] Introduce cpu_physical_memory_get_dirty_range(). X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduces cpu_physical_memory_get_dirty_range(). It checks the first row and puts dirty addr in the array. If the first row is empty, it skips to the first non-dirty row or the end addr, and put the length in the first entry of the array. Signed-off-by: Yoshiaki Tamura Signed-off-by: OHMURA Kei --- cpu-all.h | 4 +++ exec.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+), 0 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 0f5bfbe..791d91f 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -983,6 +983,10 @@ static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start, } } +int cpu_physical_memory_get_dirty_range(ram_addr_t start, ram_addr_t end, + ram_addr_t *dirty_rams, int length, + int dirty_flags); + void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, int dirty_flags); void cpu_tlb_update_dirty(CPUState *env); diff --git a/exec.c b/exec.c index 9733892..5d4171a 100644 --- a/exec.c +++ b/exec.c @@ -2045,6 +2045,72 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, } } +/* It checks the first row and puts dirty addrs in the array. + If the first row is empty, it skips to the first non-dirty row + or the end addr, and put the length in the first entry of the array. */ +int cpu_physical_memory_get_dirty_range(ram_addr_t start, ram_addr_t end, + ram_addr_t *dirty_rams, int length, + int dirty_flag) +{ + unsigned long p = 0, page_number; + ram_addr_t addr; + int s_idx = (start >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int e_idx = (end >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int i, j, offset; + + /* mask bits before the start addr */ + offset = (start >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + p |= phys_ram_dirty[MASTER_DIRTY_FLAG][s_idx] & ~((1UL << offset) - 1); + p |= phys_ram_dirty[dirty_flag][s_idx] & ~((1UL << offset) - 1); + + if (s_idx == e_idx) { + /* mask bits after the end addr */ + offset = (end >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + p &= (1UL << offset) - 1; + } + + if (p == 0) { + /* when the row is empty */ + ram_addr_t skip; + if (s_idx == e_idx) + skip = end; + else { + /* skip empty rows */ + while (s_idx < e_idx) { + s_idx++; + if ((phys_ram_dirty[MASTER_DIRTY_FLAG][s_idx] | + phys_ram_dirty[dirty_flag][s_idx]) != 0) { + break; + } + } + skip = (s_idx * HOST_LONG_BITS * TARGET_PAGE_SIZE); + } + dirty_rams[0] = skip - start; + i = 0; + + } else if (p == ~0UL) { + /* when the row is fully dirtied */ + addr = start; + for (i = 0; i < length; i++) { + dirty_rams[i] = addr; + addr += TARGET_PAGE_SIZE; + } + } else { + /* when the row is partially dirtied */ + i = 0; + do { + j = ffsl(p) - 1; + p &= ~(1UL << j); + page_number = s_idx * HOST_LONG_BITS + j; + addr = page_number * TARGET_PAGE_SIZE; + dirty_rams[i] = addr; + i++; + } while (p != 0 && i < length); + } + + return i; +} + /* Note: start and end must be within the same ram block. */ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, int dirty_flags)