From patchwork Tue Apr 6 00:51:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshiaki Tamura X-Patchwork-Id: 49474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6B0F6B7D17 for ; Tue, 6 Apr 2010 11:03:12 +1000 (EST) Received: from localhost ([127.0.0.1]:39987 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NyxC9-0003aF-LB for incoming@patchwork.ozlabs.org; Mon, 05 Apr 2010 21:03:09 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nyx6L-0001uC-8L for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:57:09 -0400 Received: from [140.186.70.92] (port=43948 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nyx6H-0001tL-WC for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:57:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nyx6C-0001fx-PR for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:57:05 -0400 Received: from sh.osrg.net ([192.16.179.4]:60018) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nyx6B-0001eq-EA for qemu-devel@nongnu.org; Mon, 05 Apr 2010 20:56:59 -0400 Received: from fs.osrg.net (postfix@fs.osrg.net [10.0.0.12]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o360uomh018682; Tue, 6 Apr 2010 09:56:50 +0900 Received: from localhost (hype-wd0.osrg.net [10.72.1.16]) by fs.osrg.net (Postfix) with ESMTP id 2FA9A3E02EC; Tue, 6 Apr 2010 09:56:50 +0900 (JST) From: Yoshiaki Tamura To: kvm@vger.kernel.org, qemu-devel@nongnu.org Date: Tue, 6 Apr 2010 09:51:21 +0900 Message-Id: <1270515084-24120-4-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Mailer: git-send-email 1.7.0.31.g1df487 In-Reply-To: <1270515084-24120-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> References: <1270515084-24120-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Dispatcher: imput version 20070423(IM149) Lines: 124 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Tue, 06 Apr 2010 09:56:52 +0900 (JST) X-Virus-Scanned: clamav-milter 0.95.3 at sh X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aliguori@us.ibm.com, ohmura.kei@lab.ntt.co.jp, mtosatti@redhat.com, Yoshiaki Tamura , avi@redhat.com Subject: [Qemu-devel] [PATCH v2 3/6] Modifies wrapper functions for byte-based phys_ram_dirty bitmap to bit-based phys_ram_dirty bitmap. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Yoshiaki Tamura Signed-off-by: OHMURA Kei --- cpu-all.h | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 67 insertions(+), 14 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index c409fad..0f5bfbe 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -891,43 +891,96 @@ extern unsigned long *phys_ram_dirty[NUM_DIRTY_FLAGS]; /* read dirty bit (return 0 or 1) */ static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; + unsigned long mask; + int index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + return (phys_ram_dirty[MASTER_DIRTY_FLAG][index] & mask) == mask; } static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS]; + unsigned long mask; + int index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + int ret = 0; + + mask = 1UL << offset; + if (phys_ram_dirty[MASTER_DIRTY_FLAG][index] & mask) + return 0xff; + if (phys_ram_dirty[VGA_DIRTY_FLAG][index] & mask) + ret |= VGA_DIRTY_FLAG; + if (phys_ram_dirty[CODE_DIRTY_FLAG][index] & mask) + ret |= CODE_DIRTY_FLAG; + if (phys_ram_dirty[MIGRATION_DIRTY_FLAG][index] & mask) + ret |= MIGRATION_DIRTY_FLAG; + + return ret; } static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, int dirty_flags) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; + unsigned long mask; + int index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + return (phys_ram_dirty[MASTER_DIRTY_FLAG][index] & mask) || + (phys_ram_dirty[dirty_flags][index] & mask); } static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) { - phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; + unsigned long mask; + int index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + phys_ram_dirty[MASTER_DIRTY_FLAG][index] |= mask; +} + +static inline void cpu_physical_memory_set_dirty_range(ram_addr_t addr, + unsigned long mask) +{ + int index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + + phys_ram_dirty[MASTER_DIRTY_FLAG][index] |= mask; } -static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr, - int dirty_flags) +static inline void cpu_physical_memory_set_dirty_flags(ram_addr_t addr, + int dirty_flags) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags; + unsigned long mask; + int index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + if (dirty_flags & VGA_DIRTY_FLAG) + phys_ram_dirty[VGA_DIRTY_FLAG][index] |= mask; + if (dirty_flags & CODE_DIRTY_FLAG) + phys_ram_dirty[CODE_DIRTY_FLAG][index] |= mask; + if (dirty_flags & MIGRATION_DIRTY_FLAG) + phys_ram_dirty[MIGRATION_DIRTY_FLAG][index] |= mask; } static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start, int length, int dirty_flags) { - int i, mask, len; - uint8_t *p; + ram_addr_t addr = start; + unsigned long mask; + int index, offset, i; + + for (i = 0; i < length; i += TARGET_PAGE_SIZE) { + index = ((addr + i) >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + offset = ((addr + i) >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + mask = ~(1UL << offset); - len = length >> TARGET_PAGE_BITS; - mask = ~dirty_flags; - p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); - for (i = 0; i < len; i++) - p[i] &= mask; + phys_ram_dirty[MASTER_DIRTY_FLAG][index] &= mask; + phys_ram_dirty[dirty_flags][index] &= mask; + } } void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,