From patchwork Sat Feb 6 16:43:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 44711 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 648C2B7D28 for ; Sun, 7 Feb 2010 03:59:55 +1100 (EST) Received: from localhost ([127.0.0.1]:52125 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NdnyQ-0002jH-CZ for incoming@patchwork.ozlabs.org; Sat, 06 Feb 2010 11:57:34 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ndnlk-00072b-24 for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:44:28 -0500 Received: from [199.232.76.173] (port=59327 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ndnlj-00072J-GR for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:44:27 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Ndnlh-0005Aw-MF for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:44:27 -0500 Received: from mx20.gnu.org ([199.232.41.8]:39490) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Ndnlg-00050R-SD for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:44:25 -0500 Received: from hall.aurel32.net ([88.191.82.174]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NdnlA-0005k2-Jy for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:43:52 -0500 Received: from [2002:52e8:2fb:1:21e:8cff:feb0:693b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NdnlA-0007r0-4A; Sat, 06 Feb 2010 17:43:52 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1Ndnl9-00065Y-E2; Sat, 06 Feb 2010 17:43:51 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 6 Feb 2010 17:43:36 +0100 Message-Id: <1265474623-23367-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1265474623-23367-1-git-send-email-aurelien@aurel32.net> References: <1265474623-23367-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by mx20.gnu.org: GNU/Linux 2.6 (newer, 3) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 1/8] sh7750: handle MMUCR TI bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When the MMUCR TI bit is set, all the UTLB and ITLB entries should be flushed. Signed-off-by: Aurelien Jarno --- hw/sh7750.c | 7 +++++-- target-sh4/cpu.h | 2 ++ target-sh4/helper.c | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index 933bbc0..9c39f4b 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -396,8 +396,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, portb_changed(s, temp); return; case SH7750_MMUCR_A7: - s->cpu->mmucr = mem_value; - return; + if (mem_value & MMUCR_TI) { + cpu_sh4_invalidate_tlb(s->cpu); + } + s->cpu->mmucr = mem_value & ~MMUCR_TI; + return; case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 366e798..015d598 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -167,6 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); +void cpu_sh4_invalidate_tlb(CPUSH4State *s); void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value); @@ -222,6 +223,7 @@ enum { /* MMU control register */ #define MMUCR 0x1F000010 #define MMUCR_AT (1<<0) +#define MMUCR_TI (1<<2) #define MMUCR_SV (1<<8) #define MMUCR_URC_BITS (6) #define MMUCR_URC_OFFSET (10) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 088d36a..e7c494f 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env) entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); } + void cpu_sh4_invalidate_tlb(CPUSH4State *s) +{ + int i; + + /* UTLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + /* ITLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + + tlb_flush(s, 1); +} + void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value) {