@@ -1077,6 +1077,7 @@ void pci_for_each_device(PCIBus *bus, int bus_num,
static void pci_device_print(Monitor *mon, QDict *device)
{
+ int class;
QDict *qdict;
QListEntry *entry;
uint64_t addr, size;
@@ -1088,10 +1089,11 @@ static void pci_device_print(Monitor *mon, QDict *device)
monitor_printf(mon, " ");
qdict = qdict_get_qdict(device, "class_info");
+ class = qdict_get_int(qdict, "class");
if (qdict_haskey(qdict, "desc")) {
monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
} else {
- monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
+ monitor_printf(mon, "Class %d", class);
}
qdict = qdict_get_qdict(device, "id");
@@ -1104,7 +1106,36 @@ static void pci_device_print(Monitor *mon, QDict *device)
qdict_get_int(device, "IRQ"));
}
- /* TODO: PCI bridge info */
+ if (qdict_haskey(device, "pci_bridge")) {
+ QDict *info;
+
+ qdict = qdict_get_qdict(device, "pci_bridge");
+
+ info = qdict_get_qdict(qdict, "bus");
+ monitor_printf(mon, " BUS %" PRId64 ".\n",
+ qdict_get_int(info, "number"));
+ monitor_printf(mon, " secondary bus %" PRId64 ".\n",
+ qdict_get_int(info, "secondary"));
+ monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
+ qdict_get_int(info, "subordinate"));
+
+ info = qdict_get_qdict(qdict, "io_range");
+ monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
+ qdict_get_int(info, "base"),
+ qdict_get_int(info, "limit"));
+
+ info = qdict_get_qdict(qdict, "memory_range");
+ monitor_printf(mon,
+ " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
+ qdict_get_int(info, "base"),
+ qdict_get_int(info, "limit"));
+
+ info = qdict_get_qdict(qdict, "prefetchable_range");
+ monitor_printf(mon, " prefetchable memory range "
+ "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
+ qdict_get_int(info, "base"),
+ qdict_get_int(info, "limit"));
+ }
QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
qdict = qobject_to_qdict(qlist_entry_obj(entry));
@@ -1202,8 +1233,9 @@ static QObject *pci_get_regions_list(const PCIDevice *dev)
return QOBJECT(regions_list);
}
-static QObject *pci_get_dev_dict(const PCIDevice *dev, int bus_num)
+static QObject *pci_get_dev_dict(PCIDevice *dev, int bus_num)
{
+ int class;
QObject *obj;
obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
@@ -1219,6 +1251,31 @@ static QObject *pci_get_dev_dict(const PCIDevice *dev, int bus_num)
qdict_put(qdict, "IRQ", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
}
+ class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
+ if (class == 0x0604) {
+ QDict *qdict;
+ QObject *pci_bridge;
+
+ pci_bridge = qobject_from_jsonf("{ 'bus': "
+ "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
+ "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
+ "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
+ "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
+ dev->config[0x19], dev->config[PCI_SECONDARY_BUS],
+ dev->config[PCI_SUBORDINATE_BUS],
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_PREFETCH),
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_PREFETCH));
+
+ qdict = qobject_to_qdict(obj);
+ qdict_put_obj(qdict, "pci_bridge", pci_bridge);
+ }
+
return obj;
}
@@ -1277,9 +1334,22 @@ static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
* - "device": device ID
* - "vendor": vendor ID
* - "qdev_id": qdev id string
+ * - "pci_bridge": It's a QDict, only present if this device is a
+ * PCI bridge, contains:
+ * - "bus": bus number
+ * - "secondary": secondary bus number
+ * - "subordinate": subordinate bus number
+ * - "io_range": a QDict with memory range information
+ * - "memory_range": a QDict with memory range information
+ * - "prefetchable_range": a QDict with memory range information
* - "regions": a QList of QDicts, each QDict represents a
* memory region of this device
*
+ * The memory range QDict contains the following:
+ *
+ * - "base": base memory address
+ * - "limit": limit value
+ *
* The region QDict can be an I/O region or a memory region,
* the I/O region contains the following:
*
This commit adds the "pci_bridge" key to the PCI device QDict, it also adds support for printing it in the user protocol. This code is being added separately because I could not test it properly. According to Michael Tsirkin, it depends on ultrasparc and it would take time to do the proper setup. Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com> --- hw/pci.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 73 insertions(+), 3 deletions(-)