| Message ID | 1255287547-28329-3-git-send-email-gleb@redhat.com |
|---|---|
| State | Not Applicable |
| Headers | show |
On Sun, Oct 11, 2009 at 08:59:05PM +0200, Gleb Natapov wrote: > Bit 0 is the enable bit, which we not only don't want to set, but > it will stick and make us think it's an I/O port resource. > > Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806 > > Signed-off-by: Gleb Natapov <gleb@redhat.com> > --- > src/pciinit.c | 8 +++++--- > 1 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/src/pciinit.c b/src/pciinit.c > index 1d0f784..29b3901 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -139,11 +139,13 @@ static void pci_bios_init_device(u16 bdf) > int ofs; > u32 val, size; > > - if (i == PCI_ROM_SLOT) > + if (i == PCI_ROM_SLOT) { > ofs = PCI_ROM_ADDRESS; > - else > + pci_config_writel(bdf, ofs, 0xfffffffe); > + } else { > ofs = PCI_BASE_ADDRESS_0 + i * 4; > - pci_config_writel(bdf, ofs, 0xffffffff); > + pci_config_writel(bdf, ofs, 0xffffffff); > + } > val = pci_config_readl(bdf, ofs); > if (val != 0) { > size = (~(val & ~0xf)) + 1; Hmm, eithe rinterpreet the spec strictly or loosely. If you implement the spec loosely, you can just write 0xfffffffe unconditionally: low bit is readonly for i/o and memory. Strict interpretation of spec requires that you write 0 into reserved bits. These are bits 1 to 10 for ROM, and bit 1 for I/O. > -- > 1.6.3.3 > >
On Sun, Oct 11, 2009 at 11:53:56PM +0200, Michael S. Tsirkin wrote: > On Sun, Oct 11, 2009 at 08:59:05PM +0200, Gleb Natapov wrote: > > Bit 0 is the enable bit, which we not only don't want to set, but > > it will stick and make us think it's an I/O port resource. > > > > Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806 > > > > Signed-off-by: Gleb Natapov <gleb@redhat.com> > > --- > > src/pciinit.c | 8 +++++--- > > 1 files changed, 5 insertions(+), 3 deletions(-) > > > > diff --git a/src/pciinit.c b/src/pciinit.c > > index 1d0f784..29b3901 100644 > > --- a/src/pciinit.c > > +++ b/src/pciinit.c > > @@ -139,11 +139,13 @@ static void pci_bios_init_device(u16 bdf) > > int ofs; > > u32 val, size; > > > > - if (i == PCI_ROM_SLOT) > > + if (i == PCI_ROM_SLOT) { > > ofs = PCI_ROM_ADDRESS; > > - else > > + pci_config_writel(bdf, ofs, 0xfffffffe); > > + } else { > > ofs = PCI_BASE_ADDRESS_0 + i * 4; > > - pci_config_writel(bdf, ofs, 0xffffffff); > > + pci_config_writel(bdf, ofs, 0xffffffff); > > + } > > val = pci_config_readl(bdf, ofs); > > if (val != 0) { > > size = (~(val & ~0xf)) + 1; > > Hmm, eithe rinterpreet the spec strictly or loosely. > > If you implement the spec loosely, you can just write > 0xfffffffe unconditionally: low bit is readonly for i/o and memory. > > Strict interpretation of spec requires that you write 0 > into reserved bits. These are bits 1 to 10 for ROM, > and bit 1 for I/O. > > Send patch with your favorite interpretation to qemu pcbios/seabios. The regression concern from my previous mail applicable here as well. -- Gleb.
diff --git a/src/pciinit.c b/src/pciinit.c index 1d0f784..29b3901 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -139,11 +139,13 @@ static void pci_bios_init_device(u16 bdf) int ofs; u32 val, size; - if (i == PCI_ROM_SLOT) + if (i == PCI_ROM_SLOT) { ofs = PCI_ROM_ADDRESS; - else + pci_config_writel(bdf, ofs, 0xfffffffe); + } else { ofs = PCI_BASE_ADDRESS_0 + i * 4; - pci_config_writel(bdf, ofs, 0xffffffff); + pci_config_writel(bdf, ofs, 0xffffffff); + } val = pci_config_readl(bdf, ofs); if (val != 0) { size = (~(val & ~0xf)) + 1;
Bit 0 is the enable bit, which we not only don't want to set, but it will stick and make us think it's an I/O port resource. Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806 Signed-off-by: Gleb Natapov <gleb@redhat.com> --- src/pciinit.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-)