diff mbox

[12/12] cpuid: decrease L2 cache for Intel and add comments

Message ID 1252621257-26364-13-git-send-email-andre.przywara@amd.com
State Superseded
Headers show

Commit Message

Andre Przywara Sept. 10, 2009, 10:20 p.m. UTC 
The Intel cache info leafs describe a Core2Duo with 4MB L2 Cache.
This is a pretty high value not reached by many host CPUs. So lower
this value to one MB to avoid guests assuming too large caches.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 target-i386/cpuid.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)
diff mbox

Patch

diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
index b35523c..7b3f31b 100644
--- a/target-i386/cpuid.c
+++ b/target-i386/cpuid.c
@@ -700,25 +700,25 @@  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
             *eax = 0;
         }
         switch (count) {
-            case 0: /* L1 dcache info */
+            case 0: /* L1 dcache info: 32KB */
                 *eax |= 0x0000121;
                 *ebx = 0x1c0003f;
                 *ecx = 0x000003f;
                 *edx = 0x0000001;
                 break;
-            case 1: /* L1 icache info */
+            case 1: /* L1 icache info: 32KB */
                 *eax |= 0x0000122;
                 *ebx = 0x1c0003f;
                 *ecx = 0x000003f;
                 *edx = 0x0000001;
                 break;
-            case 2: /* L2 cache info */
+            case 2: /* L2 cache info: 1024KB */
                 *eax |= 0x0000143;
                 if (env->nr_threads > 1) {
                     *eax |= (env->nr_threads - 1) << 14;
                 }
                 *ebx = 0x3c0003f;
-                *ecx = 0x0000fff;
+                *ecx = 0x00003ff;
                 *edx = 0x0000001;
                 break;
             default: /* end of info */
@@ -790,14 +790,14 @@  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
         break;
     case 0x80000005:
-        /* cache info (L1 cache) */
+        /* cache info (L1 cache): 64KB L1D & L1I */
         *eax = 0x01ff01ff;
         *ebx = 0x01ff01ff;
         *ecx = 0x40020140;
         *edx = 0x40020140;
         break;
     case 0x80000006:
-        /* cache info (L2 cache) */
+        /* cache info (L2 cache): 512KB L2, no L3 */
         *eax = 0;
         *ebx = 0x42004200;
         *ecx = 0x02008140;