From patchwork Wed Aug 26 11:53:34 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 32130 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id 9EB0EB70B0 for ; Wed, 26 Aug 2009 21:57:41 +1000 (EST) Received: from localhost ([127.0.0.1]:35013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MgH8C-000380-SB for incoming@patchwork.ozlabs.org; Wed, 26 Aug 2009 07:57:36 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MgH4d-0001rq-Cq for qemu-devel@nongnu.org; Wed, 26 Aug 2009 07:53:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MgH4Y-0001nM-Be for qemu-devel@nongnu.org; Wed, 26 Aug 2009 07:53:54 -0400 Received: from [199.232.76.173] (port=52126 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MgH4Y-0001nJ-5i for qemu-devel@nongnu.org; Wed, 26 Aug 2009 07:53:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:18928) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MgH4X-000530-Fq for qemu-devel@nongnu.org; Wed, 26 Aug 2009 07:53:49 -0400 Received: from int-mx05.intmail.prod.int.phx2.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.18]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n7QBrmh5001737 for ; Wed, 26 Aug 2009 07:53:48 -0400 Received: from zweiblum.home.kraxel.org (vpn1-4-183.ams2.redhat.com [10.36.4.183]) by int-mx05.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id n7QBrg9x012614; Wed, 26 Aug 2009 07:53:43 -0400 Received: by zweiblum.home.kraxel.org (Postfix, from userid 500) id 1A45A700DC; Wed, 26 Aug 2009 13:53:40 +0200 (CEST) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Wed, 26 Aug 2009 13:53:34 +0200 Message-Id: <1251287619-20022-7-git-send-email-kraxel@redhat.com> In-Reply-To: <1251287619-20022-1-git-send-email-kraxel@redhat.com> References: <1251287619-20022-1-git-send-email-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.18 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Cc: Gerd Hoffmann Subject: [Qemu-devel] [PATCH 06/11] ide: split away ide-mmio.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org create ide-mmio.c and place mmio support there. only build ide-mmio support for platforms using it. Signed-off-by: Gerd Hoffmann --- Makefile.target | 2 +- hw/ide-mmio.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/ide.c | 93 ----------------------------------------- hw/ide.h | 5 ++ hw/r2d.c | 1 + hw/sh.h | 4 -- 6 files changed, 130 insertions(+), 98 deletions(-) create mode 100644 hw/ide-mmio.c diff --git a/Makefile.target b/Makefile.target index 082a82c..9799c2a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -281,7 +281,7 @@ obj-arm-y += syborg_virtio.o obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o -obj-sh4-y += ide.o +obj-sh4-y += ide.o ide-mmio.o obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o obj-m68k-y += m68k-semi.o dummy_m68k.o diff --git a/hw/ide-mmio.c b/hw/ide-mmio.c new file mode 100644 index 0000000..07b1ccf --- /dev/null +++ b/hw/ide-mmio.c @@ -0,0 +1,123 @@ +/* + * QEMU IDE Emulation: mmio support (for embedded). + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2006 Openedhand Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "hw.h" +#include "block.h" +#include "block_int.h" +#include "sysemu.h" +#include "dma.h" +#include "ide-internal.h" + +/***********************************************************/ +/* MMIO based ide port + * This emulates IDE device connected directly to the CPU bus without + * dedicated ide controller, which is often seen on embedded boards. + */ + +typedef struct { + IDEBus *bus; + int shift; +} MMIOState; + +static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) +{ + MMIOState *s = (MMIOState*)opaque; + IDEBus *bus = s->bus; + addr >>= s->shift; + if (addr & 7) + return ide_ioport_read(bus, addr); + else + return ide_data_readw(bus, 0); +} + +static void mmio_ide_write (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MMIOState *s = (MMIOState*)opaque; + IDEBus *bus = s->bus; + addr >>= s->shift; + if (addr & 7) + ide_ioport_write(bus, addr, val); + else + ide_data_writew(bus, 0, val); +} + +static CPUReadMemoryFunc * const mmio_ide_reads[] = { + mmio_ide_read, + mmio_ide_read, + mmio_ide_read, +}; + +static CPUWriteMemoryFunc * const mmio_ide_writes[] = { + mmio_ide_write, + mmio_ide_write, + mmio_ide_write, +}; + +static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) +{ + MMIOState *s= (MMIOState*)opaque; + IDEBus *bus = s->bus; + return ide_status_read(bus, 0); +} + +static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MMIOState *s = (MMIOState*)opaque; + IDEBus *bus = s->bus; + ide_cmd_write(bus, 0, val); +} + +static CPUReadMemoryFunc * const mmio_ide_status[] = { + mmio_ide_status_read, + mmio_ide_status_read, + mmio_ide_status_read, +}; + +static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { + mmio_ide_cmd_write, + mmio_ide_cmd_write, + mmio_ide_cmd_write, +}; + +void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, + qemu_irq irq, int shift, + BlockDriverState *hd0, BlockDriverState *hd1) +{ + MMIOState *s = qemu_mallocz(sizeof(MMIOState)); + IDEBus *bus = qemu_mallocz(sizeof(*bus)); + int mem1, mem2; + + ide_init2(bus, hd0, hd1, irq); + + s->bus = bus; + s->shift = shift; + + mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); + mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); + cpu_register_physical_memory(membase, 16 << shift, mem1); + cpu_register_physical_memory(membase2, 2 << shift, mem2); +} + diff --git a/hw/ide.c b/hw/ide.c index b313627..61ff9d2 100644 --- a/hw/ide.c +++ b/hw/ide.c @@ -2700,99 +2700,6 @@ void ide_dma_cancel(BMDMAState *bm) } } -/***********************************************************/ -/* MMIO based ide port - * This emulates IDE device connected directly to the CPU bus without - * dedicated ide controller, which is often seen on embedded boards. - */ - -typedef struct { - IDEBus *bus; - int shift; -} MMIOState; - -static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) -{ - MMIOState *s = (MMIOState*)opaque; - IDEBus *bus = s->bus; - addr >>= s->shift; - if (addr & 7) - return ide_ioport_read(bus, addr); - else - return ide_data_readw(bus, 0); -} - -static void mmio_ide_write (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - MMIOState *s = (MMIOState*)opaque; - IDEBus *bus = s->bus; - addr >>= s->shift; - if (addr & 7) - ide_ioport_write(bus, addr, val); - else - ide_data_writew(bus, 0, val); -} - -static CPUReadMemoryFunc * const mmio_ide_reads[] = { - mmio_ide_read, - mmio_ide_read, - mmio_ide_read, -}; - -static CPUWriteMemoryFunc * const mmio_ide_writes[] = { - mmio_ide_write, - mmio_ide_write, - mmio_ide_write, -}; - -static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) -{ - MMIOState *s= (MMIOState*)opaque; - IDEBus *bus = s->bus; - return ide_status_read(bus, 0); -} - -static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - MMIOState *s = (MMIOState*)opaque; - IDEBus *bus = s->bus; - ide_cmd_write(bus, 0, val); -} - -static CPUReadMemoryFunc * const mmio_ide_status[] = { - mmio_ide_status_read, - mmio_ide_status_read, - mmio_ide_status_read, -}; - -static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { - mmio_ide_cmd_write, - mmio_ide_cmd_write, - mmio_ide_cmd_write, -}; - -void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, - qemu_irq irq, int shift, - BlockDriverState *hd0, BlockDriverState *hd1) -{ - MMIOState *s = qemu_mallocz(sizeof(MMIOState)); - IDEBus *bus = qemu_mallocz(sizeof(*bus)); - int mem1, mem2; - - ide_init2(bus, hd0, hd1, irq); - - s->bus = bus; - s->shift = shift; - - mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); - mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); - cpu_register_physical_memory(membase, 16 << shift, mem1); - cpu_register_physical_memory(membase2, 2 << shift, mem2); -} - -/***********************************************************/ /* CF-ATA Microdrive */ #define METADATA_SIZE 0x20 diff --git a/hw/ide.h b/hw/ide.h index 02aa686..56cf4ec 100644 --- a/hw/ide.h +++ b/hw/ide.h @@ -19,4 +19,9 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq, void *dbdma, int channel, qemu_irq dma_irq); +/* ide-mmio.c */ +void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, + qemu_irq irq, int shift, + BlockDriverState *hd0, BlockDriverState *hd1); + #endif /* HW_IDE_H */ diff --git a/hw/r2d.c b/hw/r2d.c index ebcfbe7..4667a5d 100644 --- a/hw/r2d.c +++ b/hw/r2d.c @@ -31,6 +31,7 @@ #include "pci.h" #include "net.h" #include "sh7750_regs.h" +#include "ide.h" #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ #define SDRAM_SIZE 0x04000000 diff --git a/hw/sh.h b/hw/sh.h index 5e3c22b..d30e9f5 100644 --- a/hw/sh.h +++ b/hw/sh.h @@ -51,8 +51,4 @@ qemu_irq sh7750_irl(struct SH7750State *s); /* tc58128.c */ int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2); -/* ide.c */ -void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2, - qemu_irq irq, int shift, - BlockDriverState *hd0, BlockDriverState *hd1); #endif