From patchwork Sun Jan 12 23:33:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 309653 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 653892C007A for ; Mon, 13 Jan 2014 10:34:18 +1100 (EST) Received: from localhost ([::1]:39878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W2UXo-0000VA-05 for incoming@patchwork.ozlabs.org; Sun, 12 Jan 2014 18:34:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W2UXL-0000PZ-H9 for qemu-devel@nongnu.org; Sun, 12 Jan 2014 18:33:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W2UXD-0006Mk-3Y for qemu-devel@nongnu.org; Sun, 12 Jan 2014 18:33:47 -0500 Received: from mail-qc0-x234.google.com ([2607:f8b0:400d:c01::234]:33458) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W2UXC-0006Ma-Ub for qemu-devel@nongnu.org; Sun, 12 Jan 2014 18:33:39 -0500 Received: by mail-qc0-f180.google.com with SMTP id i17so833066qcy.39 for ; Sun, 12 Jan 2014 15:33:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=sEc+cDRs3oWPDNHErLrQJ87M/xxmq9LiRgOnhFbRpFQ=; b=cnKiPThxFmYGzMSpbVLK06rYj13MUNtUSyY5qGqUXLqKP5K95ry5Oj5rzCyIb6/o6P XbPT/SwsjHhQdU0ytGYUWuHXZHrnD884pTplGTXy/Tdl7d3H1K4mYWRJF0ZcTuW8B6jo LXB8temMwfElKKQalH7zzhi52H+chAylc3ntsuTLcLqENtySqGROLbVDh8f6z0FPnhwm ovXL/ThiKXaW4fD5PYeiy0uidnTzG8yokx2LNcDYF2XRUa515MxG680HCLA2wHmZ/6QB Tt8qdo/b3Bwh3R+Fni/2WNaAztdnn/GXbWQoSBDKEHZyJM5gETjhG+JrcuMm6IfTgwi4 AyVg== X-Received: by 10.49.39.165 with SMTP id q5mr33624971qek.48.1389569618477; Sun, 12 Jan 2014 15:33:38 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id b3sm7012600qeh.17.2014.01.12.15.33.37 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Sun, 12 Jan 2014 15:33:38 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Date: Mon, 13 Jan 2014 09:33:35 +1000 Message-Id: <0dcbbf9ba6301afde428928238a06615cf936fd0.1389326614.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::234 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH arm-midr v1 1/2] ARM: Convert MIDR to a property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the MIDR register to a property. This allows boards to later set a custom MIDR value. This has been done in such a way to maintain compatibility with all existing CPUs and boards Signed-off-by: Alistair Francis --- I added the properties to the cpu->midr variable in a similar method to how Peter Crosthwaite did in his 'Fix Support for ARM CBAR and reset-hivecs' series. target-arm/cpu.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 408d207..bf625b0 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -249,10 +249,14 @@ static Property arm_cpu_reset_cbar_property = static Property arm_cpu_reset_hivecs_property = DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); +static Property arm_cpu_midr_property = + DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0); + static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); Error *err = NULL; + uint32_t temp = cpu->midr; if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, @@ -265,6 +269,19 @@ static void arm_cpu_post_init(Object *obj) &err); assert_no_error(err); } + + /* + * Initialise the midr property and set it to the original CPU MIDR + * This is used to maintain compatibility with boards that don't set + * a custom MIDR + */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_midr_property, &err); + assert_no_error(err); + object_property_set_int(OBJECT(cpu), temp, "midr", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } } static void arm_cpu_finalizefn(Object *obj)