From patchwork Thu Feb 24 17:57:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 84480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8437EB7103 for ; Fri, 25 Feb 2011 07:29:39 +1100 (EST) Received: from localhost ([127.0.0.1]:50875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pshoe-0000Qo-GH for incoming@patchwork.ozlabs.org; Thu, 24 Feb 2011 15:29:36 -0500 Received: from [140.186.70.92] (port=39292 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PshXP-0000OI-D9 for qemu-devel@nongnu.org; Thu, 24 Feb 2011 15:11:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PshEV-0002fk-L0 for qemu-devel@nongnu.org; Thu, 24 Feb 2011 14:52:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:20093) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PshEV-0002fN-Ce for qemu-devel@nongnu.org; Thu, 24 Feb 2011 14:52:15 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p1OHwkbd010446 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 24 Feb 2011 12:58:47 -0500 Received: from trasno.mitica (ovpn-113-97.phx2.redhat.com [10.3.113.97]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p1OHw0jj014622; Thu, 24 Feb 2011 12:58:46 -0500 From: Juan Quintela To: qemu-devel@nongnu.org Date: Thu, 24 Feb 2011 18:57:32 +0100 Message-Id: <09c4042e275bf04e7082b53fa68d0a72cd87038f.1298569508.git.quintela@redhat.com> In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 35/58] vmstate: port pxa2xx_rtc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Juan Quintela --- hw/pxa2xx.c | 85 +++++++++++++++++++++++++--------------------------------- 1 files changed, 37 insertions(+), 48 deletions(-) diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 349a5d4..e6542a0 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -1170,62 +1170,53 @@ static void pxa2xx_rtc_init(PXA2xxState *s) s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); } -static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) +static void pxa2xx_rtc_pre_save(void *opaque) { - PXA2xxState *s = (PXA2xxState *) opaque; + PXA2xxState *s = opaque; pxa2xx_rtc_hzupdate(s); pxa2xx_rtc_piupdate(s); pxa2xx_rtc_swupdate(s); +} - qemu_put_be32s(f, &s->rttr); - qemu_put_be32s(f, &s->rtsr); - qemu_put_be32s(f, &s->rtar); - qemu_put_be32s(f, &s->rdar1); - qemu_put_be32s(f, &s->rdar2); - qemu_put_be32s(f, &s->ryar1); - qemu_put_be32s(f, &s->ryar2); - qemu_put_be32s(f, &s->swar1); - qemu_put_be32s(f, &s->swar2); - qemu_put_be32s(f, &s->piar); - qemu_put_be32s(f, &s->last_rcnr); - qemu_put_be32s(f, &s->last_rdcr); - qemu_put_be32s(f, &s->last_rycr); - qemu_put_be32s(f, &s->last_swcr); - qemu_put_be32s(f, &s->last_rtcpicr); - qemu_put_sbe64s(f, &s->last_hz); - qemu_put_sbe64s(f, &s->last_sw); - qemu_put_sbe64s(f, &s->last_pi); -} - -static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id) +static int pxa2xx_rtc_post_load(void *opaque, int version_id) { - PXA2xxState *s = (PXA2xxState *) opaque; - - qemu_get_be32s(f, &s->rttr); - qemu_get_be32s(f, &s->rtsr); - qemu_get_be32s(f, &s->rtar); - qemu_get_be32s(f, &s->rdar1); - qemu_get_be32s(f, &s->rdar2); - qemu_get_be32s(f, &s->ryar1); - qemu_get_be32s(f, &s->ryar2); - qemu_get_be32s(f, &s->swar1); - qemu_get_be32s(f, &s->swar2); - qemu_get_be32s(f, &s->piar); - qemu_get_be32s(f, &s->last_rcnr); - qemu_get_be32s(f, &s->last_rdcr); - qemu_get_be32s(f, &s->last_rycr); - qemu_get_be32s(f, &s->last_swcr); - qemu_get_be32s(f, &s->last_rtcpicr); - qemu_get_sbe64s(f, &s->last_hz); - qemu_get_sbe64s(f, &s->last_sw); - qemu_get_sbe64s(f, &s->last_pi); + PXA2xxState *s = opaque; pxa2xx_rtc_alarm_update(s, s->rtsr); - return 0; } +static const VMStateDescription vmstate_pxa2xx_rtc = { + .name = "pxa2xx_rtc", + .version_id = 0, + .minimum_version_id = 0, + .minimum_version_id_old = 0, + .pre_save = pxa2xx_rtc_pre_save, + .post_load = pxa2xx_rtc_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32(rttr, PXA2xxState), + VMSTATE_UINT32(rtsr, PXA2xxState), + VMSTATE_UINT32(rtar, PXA2xxState), + VMSTATE_UINT32(rdar1, PXA2xxState), + VMSTATE_UINT32(rdar2, PXA2xxState), + VMSTATE_UINT32(ryar1, PXA2xxState), + VMSTATE_UINT32(ryar2, PXA2xxState), + VMSTATE_UINT32(swar1, PXA2xxState), + VMSTATE_UINT32(swar2, PXA2xxState), + VMSTATE_UINT32(piar, PXA2xxState), + VMSTATE_UINT32(last_rcnr, PXA2xxState), + VMSTATE_UINT32(last_rdcr, PXA2xxState), + VMSTATE_UINT32(last_rycr, PXA2xxState), + VMSTATE_UINT32(last_swcr, PXA2xxState), + VMSTATE_UINT32(last_rtcpicr, PXA2xxState), + VMSTATE_INT64(last_hz, PXA2xxState), + VMSTATE_INT64(last_sw, PXA2xxState), + VMSTATE_INT64(last_pi, PXA2xxState), + VMSTATE_END_OF_LIST() + } +}; + /* I2C Interface */ typedef struct { i2c_slave i2c; @@ -2130,8 +2121,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype); pxa2xx_rtc_init(s); - register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, - pxa2xx_rtc_load, s); + vmstate_register(NULL, 0, &vmstate_pxa2xx_rtc, s); s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff); s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff); @@ -2253,8 +2243,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype); pxa2xx_rtc_init(s); - register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, - pxa2xx_rtc_load, s); + vmstate_register(NULL, 0, &vmstate_pxa2xx_rtc, s); s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff); s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);