From patchwork Thu Sep 13 20:12:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Baron X-Patchwork-Id: 183732 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AE7202C008B for ; Fri, 14 Sep 2012 07:12:11 +1000 (EST) Received: from localhost ([::1]:46799 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCGhl-0002Ry-P1 for incoming@patchwork.ozlabs.org; Thu, 13 Sep 2012 17:12:09 -0400 Received: from eggs.gnu.org ([208.118.235.92]:53388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCFmR-0001Kn-1L for qemu-devel@nongnu.org; Thu, 13 Sep 2012 16:13:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TCFmL-0002xm-46 for qemu-devel@nongnu.org; Thu, 13 Sep 2012 16:12:54 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCFmK-0002xN-RZ for qemu-devel@nongnu.org; Thu, 13 Sep 2012 16:12:49 -0400 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q8DKClpg006130 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 13 Sep 2012 16:12:47 -0400 Received: from redhat.com (dhcp-185-114.bos.redhat.com [10.16.185.114]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q8DKClkO023953; Thu, 13 Sep 2012 16:12:47 -0400 Date: Thu, 13 Sep 2012 16:12:47 -0400 From: Jason Baron To: qemu-devel@nongnu.org Message-Id: <057c93b4be1cc933dab09e3ef9bdddcaeff57fc4.1347561356.git.jbaron@redhat.com> In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: aliguori@us.ibm.com, alex.williamson@redhat.com, mst@redhat.com, jan.kiszka@siemens.com, agraf@suse.de, armbru@redhat.com, yamahata@valinux.co.jp, juzhang@redhat.com, kevin@koconnor.net, avi@redhat.com, mkletzan@redhat.com, lcapitulino@redhat.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Isaku Yamahata This was totally off: The CC registers are 16 bit (stored as little endian), their offsets run in reverse order, and D26IR as well as D25IR have 4 bytes offset to their successors. Reported-by: Jan Kiszka Signed-off-by: Isaku Yamahata Signed-off-by: Jason Baron --- hw/q35.c | 29 ++++++++++++++++++++--------- 1 files changed, 20 insertions(+), 9 deletions(-) diff --git a/hw/q35.c b/hw/q35.c index 8b6a2e5..295344e 100644 --- a/hw/q35.c +++ b/hw/q35.c @@ -474,7 +474,7 @@ static void ich9_lpc_reset(DeviceState *qdev); * Although it's not pci configuration space, it's little endian as Intel. */ -static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir) +static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) { int intx; for (intx = 0; intx < PCI_NUM_PINS; intx++) { @@ -485,15 +485,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir) static void ich9_cc_update(ICH9_LPCState *lpc) { int slot; - int reg_offset; - int intx; + int pci_intx; + + const int reg_offsets[] = { + ICH9_CC_D25IR, + ICH9_CC_D26IR, + ICH9_CC_D27IR, + ICH9_CC_D28IR, + ICH9_CC_D29IR, + ICH9_CC_D30IR, + ICH9_CC_D31IR, + }; + const int *offset; /* D{25 - 31}IR, but D30IR is read only to 0. */ - for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) { - if (slot != 30) { - ich9_cc_update_ir(lpc->irr[slot], - lpc->chip_config[ICH9_CC_D31IR + reg_offset]); + for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { + if (slot == 30) { + continue; } + ich9_cc_update_ir(lpc->irr[slot], + pci_get_word(lpc->chip_config + *offset)); } /* @@ -502,8 +513,8 @@ static void ich9_cc_update(ICH9_LPCState *lpc) * are connected to pirq lines. Our choice is PIRQ[E-H]. * INT[A-D] are connected to PIRQ[E-H] */ - for (intx = 0; intx < PCI_NUM_PINS; intx++) { - lpc->irr[30][intx] = intx + 4; + for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { + lpc->irr[30][pci_intx] = pci_intx + 4; } }