From patchwork Mon Oct 8 04:18:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 189894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 333EC2C0199 for ; Mon, 8 Oct 2012 16:03:07 +1100 (EST) Received: from localhost ([::1]:53450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4or-0003Le-UZ for incoming@patchwork.ozlabs.org; Mon, 08 Oct 2012 00:19:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:41496) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4oO-00020i-A9 for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:19:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TL4oN-0006nv-3r for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:19:24 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:64196) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4oM-0006Z2-Tl for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:19:23 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so3690214pbb.4 for ; Sun, 07 Oct 2012 21:19:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=ucFZvYCtzhWUz6QgAH5Hh4NMN55R0llpLjsm3dTd6OY=; b=VQhSWqi/IsmUl8bWkv4HFswhUUigpvuPwFVGMu8IyX56usAgXNDLMGg8zwZQ4CBQfc 1XST3GdCrq8KUFF52vRutZzdqpIdD/eRj1eDUITg8rPATHwVpD7eX0FZTzx1AxhEXNep zcFIi3q0HaM0S2Ny5NP8CEHr5EeJpcDBhkYTgPGDZ/DQww8sCm8f8238dyiWNNNz6vQO DSF8f/cbx7L3S8pB3M/owj9BImyLPdwYjYJxWl/yQlyAFIMjumrDDo4fJLoFOyAv6YKN qGEiZNIS866AAHHn2fJADF73jx3d7eIU0/Zj9cV3Kq9eJCGqM68/b0Fb1D2HHdSxB575 6dcA== Received: by 10.66.77.70 with SMTP id q6mr40246693paw.24.1349669962504; Sun, 07 Oct 2012 21:19:22 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id oj1sm3097864pbb.19.2012.10.07.21.19.19 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 07 Oct 2012 21:19:21 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, peter.maydell@linaro.org Date: Mon, 8 Oct 2012 14:18:18 +1000 Message-Id: <00d2bf9effadd8f4382903b6e2dfa2df984aee43.1349663471.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQkIZcYpRgy9/RnxL/z6oTogp9EVxv3uotjHP1Ljxq353Xq1XYZSUiocrVeDw2F3JYrWfSxf X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: "Peter A. G. Crosthwaite" Subject: [Qemu-devel] [PATCH v9 04/13] qdev: allow multiple qdev_init_gpio_in() calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Allow multiple qdev_init_gpio_in() calls for the one device. The first call will define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled with different handlers. Needed when two levels of the QOM class heirachy both define GPIO functionality, as a single GPIO handler with an index selecter is not possible. Signed-off-by: Peter A. G. Crosthwaite Reviewed-by: Peter Maydell --- changed since v7: fixed function proto identation s/g_new0/g_new/ for consistency with g_renew fixed free'ing behaviour by g_renewing "p" as well changed since v5: moved implementation to irq.c as per PMM review hw/irq.c | 27 ++++++++++++++++++++------- hw/irq.h | 11 ++++++++++- hw/qdev.c | 6 +++--- 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/irq.c b/hw/irq.c index d413a0b..f4e2a78 100644 --- a/hw/irq.c +++ b/hw/irq.c @@ -38,24 +38,37 @@ void qemu_set_irq(qemu_irq irq, int level) irq->handler(irq->opaque, irq->n, level); } -qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) +qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, + void *opaque, int n) { qemu_irq *s; struct IRQState *p; int i; - s = (qemu_irq *)g_malloc0(sizeof(qemu_irq) * n); - p = (struct IRQState *)g_malloc0(sizeof(struct IRQState) * n); - for (i = 0; i < n; i++) { - p->handler = handler; - p->opaque = opaque; - p->n = i; + if (!old) { + n_old = 0; + } + s = old ? g_renew(qemu_irq, old, n + n_old) : g_new(qemu_irq, n); + p = old ? g_renew(struct IRQState, s[0], n + n_old) : + g_new(struct IRQState, n); + for (i = 0; i < n + n_old; i++) { + if (i >= n_old) { + p->handler = handler; + p->opaque = opaque; + p->n = i; + } s[i] = p; p++; } return s; } +qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) +{ + return qemu_extend_irqs(NULL, 0, handler, opaque, n); +} + + void qemu_free_irqs(qemu_irq *s) { g_free(s[0]); diff --git a/hw/irq.h b/hw/irq.h index 56c55f0..e640c10 100644 --- a/hw/irq.h +++ b/hw/irq.h @@ -23,8 +23,17 @@ static inline void qemu_irq_pulse(qemu_irq irq) qemu_set_irq(irq, 0); } -/* Returns an array of N IRQs. */ +/* Returns an array of N IRQs. Each IRQ is assigned the argument handler and + * opaque data. + */ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n); + +/* Extends an Array of IRQs. Old IRQs have their handlers and opaque data + * preserved. New IRQs are assigned the argument handler and opaque data. + */ +qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, + void *opaque, int n); + void qemu_free_irqs(qemu_irq *s); /* Returns a new IRQ with opposite polarity. */ diff --git a/hw/qdev.c b/hw/qdev.c index b6e9207..9b9aba3 100644 --- a/hw/qdev.c +++ b/hw/qdev.c @@ -285,9 +285,9 @@ BusState *qdev_get_parent_bus(DeviceState *dev) void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n) { - assert(dev->num_gpio_in == 0); - dev->num_gpio_in = n; - dev->gpio_in = qemu_allocate_irqs(handler, dev, n); + dev->gpio_in = qemu_extend_irqs(dev->gpio_in, dev->num_gpio_in, handler, + dev, n); + dev->num_gpio_in += n; } void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n)