Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1401 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
MAINTAINERS: Add common-user/host/riscv to RISC-V section MAINTAINERS: Add common-user/host/riscv to RISC-V section - - 1 - --- 2025-04-22 Alistair Francis New
[PULL,1/1] docs: deprecate RISC-V default machine option [PULL,1/1] docs: deprecate RISC-V default machine option - - 3 - --- 2025-04-07 Alistair Francis New
[PULL,0/1] riscv-to-apply queue - - - - --- 2025-04-07 Alistair Francis New
[PULL,3/3] Revert "target/riscv/kvm: add missing KVM CSRs" [PULL,1/3] docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file. - - - - --- 2025-03-28 Alistair Francis New
[PULL,2/3] docs/specs/riscv-iommu: Fixed broken link to external risv iommu document [PULL,1/3] docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file. - - 1 - --- 2025-03-28 Alistair Francis New
[PULL,1/3] docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file. [PULL,1/3] docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file. - - 1 - --- 2025-03-28 Alistair Francis New
[PULL,0/3] riscv-to-apply queue - - - - --- 2025-03-28 Alistair Francis New
[PULL,10/10] target/riscv: Add check for 16-bit aligned PC for different priv versions. [PULL,01/10] docs/about/emulation: Fix broken link - - 1 - --- 2025-03-19 Alistair Francis New
[PULL,09/10] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall [PULL,01/10] docs/about/emulation: Fix broken link - 1 1 - --- 2025-03-19 Alistair Francis New
[PULL,08/10] target/riscv: fix handling of nop for vstart >= vl in some vector instruction [PULL,01/10] docs/about/emulation: Fix broken link - 1 1 - --- 2025-03-19 Alistair Francis New
[PULL,07/10] target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter [PULL,01/10] docs/about/emulation: Fix broken link - 1 1 - --- 2025-03-19 Alistair Francis New
[PULL,06/10] target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth() [PULL,01/10] docs/about/emulation: Fix broken link - 1 1 - --- 2025-03-19 Alistair Francis New
[PULL,05/10] hw/riscv/riscv-iommu: Fix process directory table walk [PULL,01/10] docs/about/emulation: Fix broken link - - 1 - --- 2025-03-19 Alistair Francis New
[PULL,04/10] target/riscv: fixes a bug against `ssamoswap` behavior in M-mode [PULL,01/10] docs/about/emulation: Fix broken link - 1 1 - --- 2025-03-19 Alistair Francis New
[PULL,03/10] target/riscv: fix access permission checks for CSR_SSP [PULL,01/10] docs/about/emulation: Fix broken link - 1 1 - --- 2025-03-19 Alistair Francis New
[PULL,02/10] optimize the memory probing for vector fault-only-first loads. [PULL,01/10] docs/about/emulation: Fix broken link - - 1 - --- 2025-03-19 Alistair Francis New
[PULL,01/10] docs/about/emulation: Fix broken link [PULL,01/10] docs/about/emulation: Fix broken link - - 2 - --- 2025-03-19 Alistair Francis New
[PULL,00/10] riscv-to-apply queue - - - - --- 2025-03-19 Alistair Francis New
[PULL,59/59] target/riscv/kvm: add missing KVM CSRs [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - 1 - --- 2025-03-05 Alistair Francis New
[PULL,58/59] target/riscv/kvm: add kvm_riscv_reset_regs_csr() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,57/59] target/riscv/cpu: remove unneeded !kvm_enabled() check [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,56/59] hw/intc/aplic: refine kvm_msicfgaddr [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,55/59] hw/intc/aplic: refine the APLIC realize [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,54/59] hw/intc/imsic: refine the IMSIC realize [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,53/59] binfmt: Add --ignore-family option [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,52/59] binfmt: Normalize host CPU architecture [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,51/59] binfmt: Shuffle things around [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,50/59] target/riscv/kvm: Add some exts support [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,49/59] docs/specs/riscv-iommu.rst: add HPM support info [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,48/59] hw/riscv: add IOMMU HPM trace events [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,47/59] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,46/59] hw/riscv/riscv-iommu: add hpm events mmio write [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,45/59] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,44/59] hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,43/59] hw/riscv/riscv-iommu: instantiate hpm_timer [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,42/59] hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,41/59] hw/riscv/riscv-iommu: add riscv-iommu-hpm file [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,40/59] hw/riscv/riscv-iommu-bits.h: HPM bits [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,39/59] hw/riscv/riscv-iommu.h: add missing headers [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,38/59] target/riscv/kvm: add extensions after 6.14-rc3 update [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,37/59] target/riscv/cpu.c: create flag for ziccrse [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,36/59] linux-headers: Update to Linux v6.14-rc3 [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - - - --- 2025-03-05 Alistair Francis New
[PULL,35/59] target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,34/59] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,33/59] target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,32/59] target/riscv: Mask out upper sscofpmf bits during validation [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - 1 - --- 2025-03-05 Alistair Francis New
[PULL,31/59] target/riscv: Fix the hpmevent mask [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - 1 - --- 2025-03-05 Alistair Francis New
[PULL,30/59] disas/riscv: Add missing Sdtrig CSRs [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,29/59] disas/riscv: Fix minor whitespace issues [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,28/59] target/riscv: log guest errors when reserved bits are set in PTEs [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,27/59] target/riscv: machine: Add Control Transfer Record state description [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,26/59] target/riscv: Add CTR sctrclr instruction. [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,25/59] target/riscv: Add support to record CTR entries. [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,24/59] target/riscv: Add support for Control Transfer Records extension CSRs. [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,23/59] target/riscv: Add Control Transfer Records CSR definitions. [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,22/59] target/riscv: Remove obsolete sfence.vm instruction [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,21/59] MAINTAINERS: Remove Bin Meng from RISC-V maintainers [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() 1 - - - --- 2025-03-05 Alistair Francis New
[PULL,20/59] hw/riscv/virt: Add serial alias in DTB [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,19/59] goldfish_rtc: Fix tick_offset migration [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 1 - --- 2025-03-05 Alistair Francis New
[PULL,18/59] hw/riscv/riscv-iommu-bits: Remove duplicate definitions [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 3 - --- 2025-03-05 Alistair Francis New
[PULL,17/59] hw/riscv/riscv-iommu: Remove redundant struct members [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 3 - --- 2025-03-05 Alistair Francis New
[PULL,16/59] target/riscv: add RVA23S64 profile [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,15/59] target/riscv: add RVA23U64 profile [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,14/59] target/riscv: change priv_ver check in validate_profile() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,13/59] target/riscv: add profile u_parent and s_parent [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,12/59] target/riscv: use RVB in RVA22U64 [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,11/59] target/riscv: add ssu64xl [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,10/59] hw/intc/riscv_aplic: Remove redundant "hart_idx" masking [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,09/59] target/riscv: throw debug exception before page fault [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - - 2 - --- 2025-03-05 Alistair Francis New
[PULL,08/59] target/riscv/debug.c: use wp size = 4 for 32-bit CPUs [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 2 - --- 2025-03-05 Alistair Francis New
[PULL,07/59] target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 1 - --- 2025-03-05 Alistair Francis New
[PULL,06/59] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is… [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 2 1 - --- 2025-03-05 Alistair Francis New
[PULL,05/59] target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 1 - --- 2025-03-05 Alistair Francis New
[PULL,04/59] target/riscv/csr.c: fix deadcode in aia_smode32() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 1 - --- 2025-03-05 Alistair Francis New
[PULL,03/59] target/riscv/csr.c: fix deadcode in rmw_xiregi() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 1 - --- 2025-03-05 Alistair Francis New
[PULL,02/59] target/riscv/csr.c: fix 'ret' deadcode in rmw_xireg() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 1 - --- 2025-03-05 Alistair Francis New
[PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() - 1 1 - --- 2025-03-05 Alistair Francis New
[PULL,00/59] riscv-to-apply queue - - - - --- 2025-03-05 Alistair Francis New
hw/char: sifive_uart: Free fifo on unrealize hw/char: sifive_uart: Free fifo on unrealize - - 2 1 --- 2025-03-03 Alistair Francis New
MAINTAINERS: Remove Bin Meng from RISC-V maintainers MAINTAINERS: Remove Bin Meng from RISC-V maintainers 1 - - - --- 2025-01-28 Alistair Francis New
[PULL,v2,50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0 [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,47/50] target/riscv: Add Smdbltrp ISA extension enable switch [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,46/50] target/riscv: Implement Smdbltrp behavior [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,44/50] target/riscv: Add Smdbltrp CSRs handling [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,43/50] target/riscv: Add Ssdbltrp ISA extension enable switch [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,42/50] target/riscv: Implement Ssdbltrp exception handling [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,40/50] target/riscv: Add Ssdbltrp CSRs handling [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 2 - --- 2025-01-19 Alistair Francis New
[PULL,v2,39/50] target/riscv: Fix henvcfg potentially containing stale bits [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 2 - --- 2025-01-19 Alistair Francis New
[PULL,v2,38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names 1 - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,37/50] target/riscv: Add implied rule for counter delegation extensions [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names 1 - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,36/50] target/riscv: Invoke pmu init after feature enable [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,35/50] target/riscv: Add counter delegation/configuration support [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names 1 - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,34/50] target/riscv: Add select value range check for counter delegation [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,33/50] target/riscv: Add counter delegation definitions [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 1 - --- 2025-01-19 Alistair Francis New
[PULL,v2,32/50] target/riscv: Add properties for counter delegation ISA extensions [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names - - 2 - --- 2025-01-19 Alistair Francis New
[PULL,v2,31/50] target/riscv: Support generic CSR indirect access [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names 1 - 1 - --- 2025-01-19 Alistair Francis New
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