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LIU Zhiwei
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| 206 patches
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Apply
«
1
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v4,3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 1 2 -
-
-
-
2024-07-08
LIU Zhiwei
New
[v4,2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-08
LIU Zhiwei
New
[v4,1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-08
LIU Zhiwei
New
[v3,7/7] tests/avocado: Add an avocado test for riscv64
target/riscv: Expose RV32 cpu to RV64 QEMU
1 - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 1 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,7/7] tests/avocado: Add an avocado test for riscv64
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 1 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v2,1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,11/11] disas/riscv: Support zabha disassemble
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,10/11] target/riscv: Expose zabha extension as a cpu property
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,09/11] target/riscv: Add amocas.[b|h] for Zabha
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,07/11] target/riscv: Add AMO instructions for Zabha
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,06/11] target/riscv: Move gen_amo before implement Zabha
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,05/11] target/riscv: Support Zama16b extension
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,04/11] disas/riscv: Support zcmop disassemble
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,03/11] target/riscv: Add zcmop extension
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,02/11] disas/riscv: Support zimop disassemble
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - 1 -
-
-
-
2024-07-03
LIU Zhiwei
New
[v3,01/11] target/riscv: Add zimop extension
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 2 -
-
-
-
2024-07-03
LIU Zhiwei
New
[6/6] target/riscv: Enable RV32 CPU support in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-01
LIU Zhiwei
New
[5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-01
LIU Zhiwei
New
[4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 1 -
-
-
-
2024-07-01
LIU Zhiwei
New
[3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 1 1 -
-
-
-
2024-07-01
LIU Zhiwei
New
[2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-01
LIU Zhiwei
New
[1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Expose RV32 cpu to RV64 QEMU
- - 2 -
-
-
-
2024-07-01
LIU Zhiwei
New
[v2,11/11] disas/riscv: Support zabha disassemble
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,10/11] target/riscv: Enable zabha for max cpu
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,09/11] target/riscv: Add amocas.[b|h] for Zabha
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,07/11] target/riscv: Add AMO instructions for Zabha
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,06/11] target/riscv: Move gen_amo before implement Zabha
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,05/11] target/riscv: Support Zama16b extension
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,04/11] disas/riscv: Support zcmop disassemble
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,03/11] target/riscv: Add zcmop extension
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,02/11] disas/riscv: Support zimop disassemble
target/riscv: Support zimop/zcmop/zama16b/zabha
1 - - -
-
-
-
2024-06-30
LIU Zhiwei
New
[v2,01/11] target/riscv: Add zimop extension
target/riscv: Support zimop/zcmop/zama16b/zabha
- - 1 -
-
-
-
2024-06-30
LIU Zhiwei
New
[6/6] disas/riscv: Support zabha disassemble
target/riscv: Support Zabha extension
1 - - -
-
-
-
2024-05-23
LIU Zhiwei
New
[5/6] target/riscv: Enable zabha for max cpu
target/riscv: Support Zabha extension
- - - -
-
-
-
2024-05-23
LIU Zhiwei
New
[4/6] target/riscv: Add amocas.[b|h] for Zabha
target/riscv: Support Zabha extension
- - 1 -
-
-
-
2024-05-23
LIU Zhiwei
New
[3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
target/riscv: Support Zabha extension
1 - - -
-
-
-
2024-05-23
LIU Zhiwei
New
[2/6] target/riscv: Add AMO instructions for Zabha
target/riscv: Support Zabha extension
1 - - -
-
-
-
2024-05-23
LIU Zhiwei
New
[1/6] target/riscv: Move gen_amo before implement Zabha
target/riscv: Support Zabha extension
1 - - -
-
-
-
2024-05-23
LIU Zhiwei
New
[1/1] target/riscv: Support Zama16b extension
[1/1] target/riscv: Support Zama16b extension
- - - -
-
-
-
2024-05-22
LIU Zhiwei
New
[4/4] disas/riscv: Support zcmop disassemble
target/riscv: Implement May-Be-Operations(zimop) extension
1 - - -
-
-
-
2024-05-22
LIU Zhiwei
New
[3/4] target/riscv: Add zcmop extension
target/riscv: Implement May-Be-Operations(zimop) extension
- - 1 -
-
-
-
2024-05-22
LIU Zhiwei
New
[2/4] disas/riscv: Support zimop disassemble
target/riscv: Implement May-Be-Operations(zimop) extension
1 - - -
-
-
-
2024-05-22
LIU Zhiwei
New
[1/4] target/riscv: Add zimop extension
target/riscv: Implement May-Be-Operations(zimop) extension
- - 1 -
-
-
-
2024-05-22
LIU Zhiwei
New
target/riscv: Enable xtheadsync under user mode
target/riscv: Enable xtheadsync under user mode
1 - - -
-
-
-
2024-02-04
LIU Zhiwei
New
[v2,2/2] target/riscv: Support xtheadmaee for thead-c906
target/riscv: Support mxstatus CSR for thead-c906
- - - -
-
-
-
2024-02-04
LIU Zhiwei
New
[v2,1/2] target/riscv: Register vendors CSR
target/riscv: Support mxstatus CSR for thead-c906
- - - -
-
-
-
2024-02-04
LIU Zhiwei
New
[2/2] target/riscv: Support xtheadmaee for thead-c906
target/riscv: Support mxstatus CSR for thead-c906
- - - -
-
-
-
2024-01-30
LIU Zhiwei
New
[1/2] target/riscv: Register vendors CSR
target/riscv: Support mxstatus CSR for thead-c906
- - - -
-
-
-
2024-01-30
LIU Zhiwei
New
target/riscv: FCSR doesn't contain vxrm and vxsat
target/riscv: FCSR doesn't contain vxrm and vxsat
- - 1 -
-
-
-
2024-01-30
LIU Zhiwei
New
target/riscv: Use RISCVException as return type for all csr ops
target/riscv: Use RISCVException as return type for all csr ops
- - 2 -
-
-
-
2024-01-30
LIU Zhiwei
New
[1/1] target/riscv: Not allow write mstatus_vs without RVV
[1/1] target/riscv: Not allow write mstatus_vs without RVV
- - 1 -
-
-
-
2023-12-15
LIU Zhiwei
New
[for,8.2] target/riscv: Fix th.dcache.cval1 priviledge check
[for,8.2] target/riscv: Fix th.dcache.cval1 priviledge check
- - 2 -
-
-
-
2023-12-08
LIU Zhiwei
New
[for,8.2] accel/tcg/cputlb: Fix iotlb page alignment check
[for,8.2] accel/tcg/cputlb: Fix iotlb page alignment check
- 1 - -
-
-
-
2023-12-08
LIU Zhiwei
New
[v2] qemu/timer: Add host ticks function for RISC-V
[v2] qemu/timer: Add host ticks function for RISC-V
- - - -
-
-
-
2023-09-11
LIU Zhiwei
New
[RESEND] qemu/timer: Add host ticks function for RISC-V
[RESEND] qemu/timer: Add host ticks function for RISC-V
- - - -
-
-
-
2023-09-08
LIU Zhiwei
New
qemu/timer: Add host ticks function for RISC-V
qemu/timer: Add host ticks function for RISC-V
- - - -
-
-
-
2023-09-08
LIU Zhiwei
New
[1/1] accel/tcg: Fix the comment for CPUTLBEntryFull
[1/1] accel/tcg: Fix the comment for CPUTLBEntryFull
- - 1 -
-
-
-
2023-09-01
LIU Zhiwei
New
[RFC,v2,6/6] linux-user: Move qemu_cpu_opts to cpu.c
Add API for list cpu extensions
- - - -
-
-
-
2023-08-28
LIU Zhiwei
New
[RFC,v2,5/6] target/riscv: Add defalut value for string property
Add API for list cpu extensions
- - - -
-
-
-
2023-08-28
LIU Zhiwei
New
[RFC,v2,4/6] target/riscv: Add default value for misa property
Add API for list cpu extensions
- - 1 -
-
-
-
2023-08-28
LIU Zhiwei
New
[RFC,v2,3/6] softmmu/vl: Add qemu_cpu_opts QemuOptsList
Add API for list cpu extensions
- - - -
-
-
-
2023-08-28
LIU Zhiwei
New
[RFC,v2,2/6] target/riscv: Add API list_cpu_props
Add API for list cpu extensions
- - - -
-
-
-
2023-08-28
LIU Zhiwei
New
[RFC,v2,1/6] cpu: Add new API cpu_type_by_name
Add API for list cpu extensions
- - - -
-
-
-
2023-08-28
LIU Zhiwei
New
[RFC,3/3] softmmu/vl: Add qemu_cpu_opts QemuOptsList
Add API for list cpu extensions
- - - -
-
-
-
2023-08-25
LIU Zhiwei
New
[RFC,2/3] target/riscv: Add API list_cpu_props
Add API for list cpu extensions
- - - -
-
-
-
2023-08-25
LIU Zhiwei
New
[RFC,1/3] cpu: Add new API cpu_type_by_name
Add API for list cpu extensions
- - 1 -
-
-
-
2023-08-25
LIU Zhiwei
New
[v2] linux-user/riscv: Use abi type for target_ucontext
[v2] linux-user/riscv: Use abi type for target_ucontext
- - 3 -
-
-
-
2023-08-11
LIU Zhiwei
New
linux-user/riscv: Use abi_ulong for target_ucontext
linux-user/riscv: Use abi_ulong for target_ucontext
- - 2 -
-
-
-
2023-08-08
LIU Zhiwei
New
target/riscv: Fix page_check_range use in fault-only-first
target/riscv: Fix page_check_range use in fault-only-first
- - 1 -
-
-
-
2023-07-29
LIU Zhiwei
New
target/riscv: Fix zfa fleq.d and fltq.d
target/riscv: Fix zfa fleq.d and fltq.d
- - 2 -
-
-
-
2023-07-28
LIU Zhiwei
New
fpu: Add conversions between bfloat16 and [u]int8
fpu: Add conversions between bfloat16 and [u]int8
- - - -
-
-
-
2023-05-31
LIU Zhiwei
New
[1/1] target/riscv: Convert env->virt to a bool env->virt_enabled
[1/1] target/riscv: Convert env->virt to a bool env->virt_enabled
- - 2 -
-
-
-
2023-03-25
LIU Zhiwei
New
target/riscv: Fix itrigger when icount is used
target/riscv: Fix itrigger when icount is used
1 - 1 -
-
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-
2023-03-24
LIU Zhiwei
New
[4/4] target/riscv: Add a tb flags field for vstart
Fix tb flags use
- - 2 -
-
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2023-03-24
LIU Zhiwei
New
[3/4] target/riscv: Encode the FS and VS on a normal way for tb flags
Fix tb flags use
- - 2 -
-
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-
2023-03-24
LIU Zhiwei
New
[2/4] target/riscv: Add a general status enum for extensions
Fix tb flags use
- - - -
-
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2023-03-24
LIU Zhiwei
New
[1/4] target/riscv: Extract virt enabled state from tb flags
Fix tb flags use
- - 2 -
-
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2023-03-24
LIU Zhiwei
New
tcg/tcg: Avoid TS_DEAD for basic block ending
tcg/tcg: Avoid TS_DEAD for basic block ending
- - - -
-
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2023-03-21
LIU Zhiwei
New
target/riscv: Fix priv version dependency for vector and zfh
target/riscv: Fix priv version dependency for vector and zfh
- - 2 -
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2023-03-21
LIU Zhiwei
New
target/riscv: Fix vslide1up.vf and vslide1down.vf
target/riscv: Fix vslide1up.vf and vslide1down.vf
- - 2 -
-
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-
2023-02-13
LIU Zhiwei
New
[1/1] tcg/riscv: Fix base regsiter for qemu_ld/st
[1/1] tcg/riscv: Fix base regsiter for qemu_ld/st
- - - -
-
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2022-10-23
LIU Zhiwei
New
[RFC,3/3] tcg/riscv: Remove a wrong optimization for addsub2
Fix some TCG RISC-V backend bugs
- - - -
-
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2022-10-20
LIU Zhiwei
New
[RFC,2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds
Fix some TCG RISC-V backend bugs
- - - -
-
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2022-10-20
LIU Zhiwei
New
[RFC,1/3] tcg/riscv: Fix base regsiter for qemu_ld/st
Fix some TCG RISC-V backend bugs
- - - -
-
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2022-10-20
LIU Zhiwei
New
[v1,4/4] target/riscv: Add itrigger_enabled field to CPURISCVState
Support native debug icount trigger
- - 1 -
-
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-
2022-10-13
LIU Zhiwei
New
[v1,3/4] target/riscv: Enable native debug itrigger
Support native debug icount trigger
- - 1 -
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-
2022-10-13
LIU Zhiwei
New
[v1,2/4] target/riscv: Add itrigger support when icount is enabled
Support native debug icount trigger
- - 1 -
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2022-10-13
LIU Zhiwei
New
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