Show patches with: Series = [v5,01/15] target/riscv: Refactor some of the generic vector functionality       |   15 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v5,15/15] target/riscv: Add Zvksed ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,14/15] crypto: Add SM4 constant parameter CK [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,13/15] crypto: Create sm4_subword [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 2 - --- 2023-06-27 Max Chou New
[v5,12/15] target/riscv: Add Zvkg ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,11/15] target/riscv: Add Zvksh ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,10/15] target/riscv: Add Zvknh ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,09/15] target/riscv: Add Zvkned ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,08/15] target/riscv: Add Zvbb ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,07/15] target/riscv: Refactor some of the generic vector functionality [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,06/15] target/riscv: Refactor translation of vector-widening instruction [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 2 - --- 2023-06-27 Max Chou New
[v5,05/15] target/riscv: Move vector translation checks [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 2 - --- 2023-06-27 Max Chou New
[v5,04/15] target/riscv: Add Zvbc ISA extension support [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - - - --- 2023-06-27 Max Chou New
[v5,03/15] target/riscv: Remove redundant "cpu_vl == 0" checks [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New
[v5,02/15] target/riscv: Refactor vector-vector translation macro [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 3 - --- 2023-06-27 Max Chou New
[v5,01/15] target/riscv: Refactor some of the generic vector functionality [v5,01/15] target/riscv: Refactor some of the generic vector functionality - - 1 - --- 2023-06-27 Max Chou New