Show patches with: Submitter = Bin Meng       |    State = Action Required       |   657 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v3,1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot - - 1 - --- 2021-01-06 Bin Meng New
[v5,2/2] hw/block: m25p80: Implement AAI-WP command support for SST flashes [v5,1/2] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2020-12-23 Bin Meng New
[v5,1/2] hw/block: m25p80: Don't write to flash if write is disabled [v5,1/2] hw/block: m25p80: Don't write to flash if write is disabled - 1 2 - --- 2020-12-23 Bin Meng New
[v2,3/3] net: checksum: Introduce fine control over checksum type [v2,1/3] net: checksum: Skip fragmented IP packets - - 1 - --- 2020-12-11 Bin Meng New
[v2,2/3] net: checksum: Add IP header checksum calculation [v2,1/3] net: checksum: Skip fragmented IP packets - - - - --- 2020-12-11 Bin Meng New
[v2,1/3] net: checksum: Skip fragmented IP packets [v2,1/3] net: checksum: Skip fragmented IP packets - - - - --- 2020-12-11 Bin Meng New
hw/block: m25p80: Fix fast read for SST flashes hw/block: m25p80: Fix fast read for SST flashes 1 - - - --- 2020-11-30 Bin Meng New
[v2] target/i386: seg_helper: Correct segement selector nullification in the RET/IRET helper [v2] target/i386: seg_helper: Correct segement selector nullification in the RET/IRET helper - - - - --- 2020-11-13 Bin Meng New
[v4] hw/riscv: microchip_pfsoc: Correct DDR memory map [v4] hw/riscv: microchip_pfsoc: Correct DDR memory map - - 1 - --- 2020-11-01 Bin Meng New
hw/9pfs: virtio-9p: Ensure config space is a multiple of 4 bytes hw/9pfs: virtio-9p: Ensure config space is a multiple of 4 bytes - - - - --- 2020-10-29 Bin Meng New
[v2,10/10] hw/riscv: microchip_pfsoc: Hook the I2C1 controller hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[RESEND,6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-27 Bin Meng New
[2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - - - --- 2020-10-27 Bin Meng New
[1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - - - --- 2020-10-27 Bin Meng New
hw/sd: Fix 2 GiB card CSD register values hw/sd: Fix 2 GiB card CSD register values - 1 - 1 --- 2020-10-25 Bin Meng New
hw/sd: Zero out function selection fields before being populated hw/sd: Zero out function selection fields before being populated - 1 1 - --- 2020-10-24 Bin Meng New
[RESEND,v2] hw/intc: Move sifive_plic.h to the include directory [RESEND,v2] hw/intc: Move sifive_plic.h to the include directory - 1 1 - --- 2020-10-13 Bin Meng New
[12/12] hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[11/12] hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[10/12] hw/riscv: Always build riscv_hart.c hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[09/12] hw/riscv: Move sifive_test model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[08/12] hw/riscv: Move sifive_uart model to hw/char hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[07/12] hw/riscv: Move riscv_htif model to hw/char hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[06/12] hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[05/12] hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[04/12] hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[03/12] hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[02/12] hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[01/12] hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[v3,16/16] hw/riscv: sifive_u: Connect a DMA controller hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,11/16] hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 3 - --- 2020-09-01 Bin Meng New
[v3,10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,09/16] hw/dma: Add SiFive platform DMA controller emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support 1 - - - --- 2020-09-01 Bin Meng New
[v3,08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,07/16] hw/sd: Add Cadence SDHCI emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support 2 - - - --- 2020-09-01 Bin Meng New
[v3,06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,03/16] target/riscv: cpu: Set reset vector based on the configured property value hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,02/16] hw/riscv: hart: Add a new 'resetvec' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,2/2] hw/sd: sd: Correct the maximum size of a Standard Capacity SD Memory Card [v3,1/2] hw/sd: sd: Fix incorrect populated function switch status data structure - 1 1 1 --- 2020-08-21 Bin Meng New
[v3,1/2] hw/sd: sd: Fix incorrect populated function switch status data structure [v3,1/2] hw/sd: sd: Fix incorrect populated function switch status data structure - 1 1 1 --- 2020-08-21 Bin Meng New
[v2,3/3] hw/sd: Add Cadence SDHCI emulation hw/sd: Add Cadence SDHCI emulation 1 - - - --- 2020-08-17 Bin Meng New
[v6,6/6] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,5/6] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,4/6] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,3/6] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,2/6] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,1/6] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 1 - --- 2020-08-03 Bin Meng New
hw/riscv: sifive_u: Add a dummy L2 cache controller device hw/riscv: sifive_u: Add a dummy L2 cache controller device - - 1 - --- 2020-07-20 Bin Meng New
hw/riscv: sifive_e: Correct debug block size hw/riscv: sifive_e: Correct debug block size - - 1 - --- 2020-07-16 Bin Meng New
[v2,2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running … [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - - - - --- 2020-07-09 Bin Meng New
[v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - - 1 - --- 2020-07-09 Bin Meng New
hw/riscv: virt: Sort the SoC memmap table entries hw/riscv: virt: Sort the SoC memmap table entries - - 1 - --- 2020-07-03 Bin Meng New
MAINTAINERS: Add an entry for OpenSBI firmware MAINTAINERS: Add an entry for OpenSBI firmware - - 1 - --- 2020-06-26 Bin Meng New
[v2,5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,1/5] target/riscv: Rename IBEX CPU init routine hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,4/4] riscv: Keep the CPU init routine names consistent [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,3/4] riscv: Generalize CPU init routine for the imacu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,2/4] riscv: Generalize CPU init routine for the gcsu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,1/4] riscv: Generalize CPU init routine for the base CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - - - --- 2020-06-08 Bin Meng New
[11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[05/15] hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[4/5] riscv/spike: Change the default bios to use generic platform image riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[1/5] roms/opensbi: Update to support building bios images for generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
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