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[RFC,v5,0/2] Support RISC-V CSR read/write in Qtest environment

Message ID 20241105142840.59617-1-ivan.klokov@syntacore.com
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Series Support RISC-V CSR read/write in Qtest environment | expand

Message

Ivan Klokov Nov. 5, 2024, 2:28 p.m. UTC 
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.

---
v5:
   - Move code from target/riscv to hw/riscv
---

Ivan Klokov (2):
  target/riscv: Add RISC-V CSR qtest support
  tests/qtest: QTest example for RISC-V CSR register

 hw/riscv/riscv_hart.c        | 65 ++++++++++++++++++++++++++++++++++++
 tests/qtest/libqtest.c       | 27 +++++++++++++++
 tests/qtest/libqtest.h       | 14 ++++++++
 tests/qtest/meson.build      |  2 +-
 tests/qtest/riscv-csr-test.c | 56 +++++++++++++++++++++++++++++++
 5 files changed, 163 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/riscv-csr-test.c